Novel Approaches to Amorphous Silicon Thin Film Transistors for Large Area Electronics
Speaker: Yifei Huang
Series: Final Public Orals
Location: Engineering Quadrangle J401
Date/Time: Tuesday, September 6, 2011, 2:00 p.m. - 4:00 p.m.
While scaling VLSI devices to ever shrinking dimensions has driven much of the improvement in performance and reduction in cost of electronic intelligence, a new set of challenges and opportunities has emerged in a drastically different regime. As systems become more and more powerful, they are no longer limited by their electronic information processing capability, but by the human-machine interface. For example, the quality and size of a video is limited by the display delivering it. Motivated by the experience of the end users, it is often desirable to make products (e.g. displays) bigger, more flexible and user friendly in general. In this regime, performance improvement and cost reduction cannot be achieved via scaling as in the traditional microelectronics field. They are achieved with novel devices structures, new materials, creative fabrication techniques and innovative functionalities. This thesis will present three such innovations in amorphous-silicon-based large area electronics.
The first is a novel amorphous silicon (a-Si) top-gate thin-film transistor (TFT) with self-aligned silicide source and drain. This structure offers performance that is on par with the best conventional bottom-gate a-Si TFTs, while providing better power efficiency and faster speed by eliminating parasitic capacitances. Furthermore, it can be fabricated with simple two-photomask process at low temperatures (~280°C), which is fully compatible with plastic substrates and less expensive than conventional fabrication processes. This device is ideal for flexible displays on future mobile computing devices. The device physics underlying this structure is explored and a model of the electron tunnel injection contact is presented.
The second is a creative fabrication technique called Self-Aligned Imprint Lithography (SAIL). Originally envisioned by HP labs, SAIL is designed to be a low-cost, high throughput way to manufacture a-Si TFT circuits. The first implementation by Hewlett Packard labs were limited bottom-gate a-Si TFTs, this thesis improved upon their work by developing a process to manufacture our top-gate a-Si TFT with self-aligned silicide source and drain. Our process involves imprinting a three-dimensional, multilayer mask structure, which replaces all photomasks and the alignment steps. The entire device is fabricated and patterned using this single imprinted mask structure, without any additional lithography. This process is ideal for low cost and high throughput roll-to-roll fabrication of top-gate amorphous silicon TFT with self-aligned silicide source/drain on plastic substrates. The details of the process and device characteristics are presented.
The third is an innovative functionality realized in the form of a non-volatile memory transistor based on a-Si technology. The memory works based on threshold voltage shifts, which result from electrons tunneling in and out of a charge trapping medium, controlled by the applied gate voltage. This device greatly extends the functionality of a-Si TFT based circuitry, by providing fully integrated and cost effective memory. One example, demonstrated in the thesis, is a novel active matrix organic light emitting diode (AMOLED) display architecture that operates without pixel refresh and capable of non-volatile storage of images. This architecture is ideal for low power and low frame rate applications.