Methodologies and Simulation Framework for Architectural Analysis and Power Management of FinFET Chip Multiprocessors
Speaker: Chun-Yi Lee
Series: Final Public Orals
Location: Engineering Quadrangle B327
Date/Time: Thursday, March 14, 2013, 11:00 a.m. - 12:30 p.m.
This dissertation presents a simulation framework, called FinCANON, for modeling power and timing to support a comprehensive design space exploration of caches and networks-on-chip (NoCs) in a chip multiprocessor system. It also describes methodologies for analyzing the impact of process, voltage, and temperature (PVT) variations on power consumption and delay. At the architecture level, it introduces a flow control mechanism to manage both the throughput and power consumption of NoCs.
FinFETs have emerged as promising substitutes for bulk CMOS at the 22nm technology node and beyond. Nevertheless, PVT variations in FinFETs lead to large spreads in delay and leakage. We have developed a FinFET design library to model the circuit-level characteristics as well as their variation trends with respect to various PVT parameters for FinFET logic gates and memory cells. Based on a statistical static timing analysis technique and macromodel based methodology, we have derived the PVT variation models for delay and leakage, taking into account spatial correlations, to characterize the impact of PVT variations on FinFET-based caches and NoCs.
Based on the FinFET design library, we next present FinCANON, an integrated framework for the simulation of power, delay, as well as PVT variations of FinFETbased caches and NoCs. FinCANON is built atop CACTI-PVT and ORION-PVT that model caches and NoCs, respectively. FinCANON enables architects to evaluate the impact of PVT variations on caches and NoCs at an early design stage. We present results for various FinFET design styles and show that mixing different styles may be a promising strategy for optimizing delay and leakage of caches and NoCs.
We next discuss the microarchitecture and flow control mechanism of a variable-pipeline-stage router (VPSR). VPSR adjusts the number of pipeline stages based on incoming traffic to a router port, leading to significant savings in leakage power while maintaining router throughput. We also propose enhanced token flow control, a flow control mechanism that improves upon the energy-delay-throughput of the previous state-of-the-art token flow control mechanism. We propose a new concept of using guaranteed tokens to establish temporary express virtual channels to quickly bypass packets from congested regions.