Mechanisms for Usable Multicores
Speaker: David Wentzlaff, Massachusetts Institute of Technology
Series: Electrical Engineering Departmental Seminar
Location: Engineering Quadrangle B205
Date/Time: Thursday, March 10, 2011, 4:30 p.m. - 5:30 p.m.
In order for the computing industry to strive and fuel human innovation, usable computation must continue to become faster and cheaper. The traditional approach of waiting for sequential processor performance to increase has broken down due to power constraints, design complexity, and techniques such as pipelining running out of steam. As a response to these problems, computer architects have turned to parallelism in the form of multicore and manycore processors where tens, hundreds, or even thousands of processor cores are being integrated onto a single chip. The design of these multicore processors and the architectural mechanisms needed to make them scale and provide usable performance to the average programmer will be key to driving the computing industry. This talk introduces two new architectural mechanisms which enable applications to utilize scalable multicore processors by solving the questions of how to protect multiple disparate systems being integrated onto a multicore processor and how to manage memory locality on a multicore processor.
This talk will describe Configurable Fine-Grain Protection (CFP) which allows multiple operating systems which have different architectural requirements to share a single multicore processor while guaranteeing both isolation and performance independence. Also, Remote Store Programming (RSP) will be presented which enables multicore programs to carefully control communication costs while still using familiar shared memory programming. All of the presented techniques will be discussed in the context of three real world systems: The 16-core MIT Raw Processor, the 64-core Tilera TILE64 Processor, and the MIT Factored Operating System (fos), a scalable operating system for future multicores and cloud systems.
David Wentzlaff is a PhD candidate at MIT and is a co-founder of Tilera Corporation. At Tilera, he was Lead Architect of the TILE64 and
TILEPro64 processors and designed the scalable TILE processor architecture. Before Tilera, he was one of the architects of the Raw Processor at MIT and designed the Raw on-chip networks. David founded the MIT Factored Operating System (fos) project and is currently designing scalable operating systems for thousand core multicores and cloud computers. David received a MS in EECS from MIT and a BS in EE from UIUC. He enjoys hiking and mountaineering when not designing multicore processors or operating systems.