Design for Robustness in Extreme Scaling and 3D-IC
Speaker: David Pan, University of Texas-Austin
Department: Electrical Engineering
Location: Engineering Quadrangle B327
Date/Time: Wednesday, March 13, 2013, 12:30 p.m. - 1:30 p.m.
As the CMOS feature enters the era of extreme scaling (14nm, 11nm and beyond), the printability challenges are exacerbated. Meanwhile, the vertical scaling with 3D-IC integration using through-silicon-vias (TSVs) has gained tremendous momentum and initial industry adoption, which can further extend Moores Law even when horizontal scaling stops ultimately. However, as TSVs involve disruptive manufacturing technologies, new modeling and design techniques need to be developed for robust 3D-IC integration. In this talk, I will first present some of our recent results on pushing the nanolithography limit with novel design techniques, for multiple patterning lithography as well as other emerging lithography technologies. In 3D ICs, TSVs may cause significant thermomechanical stress, which not only results in systematic mobility and performance variations, but also leads to mechanical and electrical reliability concerns. Ill discuss full-chip/package modeling and physical design for reliable 3D-IC integration.