Improving On-chip Communication, Power Delivery, and Computation for Next-generation VLSI Systems
Speaker: Jae-sun Seo, IBM T. J. Watson Research Center
Department: Electrical Engineering
Location: Engineering Quadrangle B327
Date/Time: Monday, November 25, 2013, 12:30 p.m. - 1:30 p.m.
Abstract: CMOS scaling is slowing down and modern VLSI systems confront power and performance challenges, necessitating improvements in circuit/system design. On-chip communication becomes the performance-limiter of large-scale computing systems, due to the ever-growing gap of transistor delays and fixed-length wire delays. I present circuit techniques including signal pre-emphasis and low-swing signaling for high-speed on-chip links. Measurements from 90nm prototype chips validate 2.5-3X improvement in energy-delay product. Another critical concern for applications ranging from servers to mobile devices is efficient power delivery and voltage regulation against fluctuating workloads. On-chip switched-capacitor down-conversion circuits enable power delivery at >2VDD voltages, significantly lowering IR distribution losses and supply noise. Utilizing high-density capacitors in advanced SOI technologies, I present design techniques in building practical integrated switched-capacitor voltage converters, including circuit optimization, chip-level floorplanning, and fast regulation.
With improvements in performance/power-limiters, more opportunities could be found for next-generation computing by exploring emerging applications (vision, accelerators, bio-inspired computing, etc.). As an exemplary work, I present a neuromorphic chip that can perform unsupervised learning on pattern recognition tasks, designed with a scalable architecture for networks of spiking neurons. Through tight integration of memory (64K synapses) and computation (256 neurons), a highly configurable 45nm chip operates at 0.53V and demonstrates on-chip learning based on spike-timing dependent plasticity. Co-optimizing circuits, computing algorithms, and architecture as shown in this work will open up possibilities for future computing systems.
Bio: Jae-sun Seo received the B.S. degree from Seoul National University, Korea, in 2001, and the M.S. and Ph.D. degree from the University of Michigan in 2006 and 2010, respectively, all in electrical engineering. Since 2010, he has been with IBM T. J. Watson Research Center, where he worked on energy-efficient integrated circuits for high-performance processors and cognitive computing chips. Starting January 2014, he will join Arizona State University as an assistant professor in the school of electrical, computer, and energy engineering. Mr. Seo was a recipient of Samsung Scholarship, received an IBM outstanding technical achievement award in 2012, and serves on the technical program committee for ISLPED.