Circuit and Microarchitecture Co-design for Power-Efficient Multi-core Processors
Speaker: Nam Sung Kim, University of Wisconsin-Madison
Department: Electrical Engineering
Location: Engineering Quadrangle B205
Date/Time: Tuesday, April 17, 2012, 4:30 p.m. - 5:30 p.m.
In this talk, I present two circuit and microarchitecture co-design techniques for power-efficient multi-core processors. First, I present a technique for last-level-caches (LLCs) supporting low minimum operating voltage (VDDMIN) cost-effectively. In this technique, I exploit (i) the DVFS characteristics of workloads running on high-performance processors, (ii) the trade-off between SRAM cell size and VDDMIN, and 3) the fact that at lower voltage/frequency operating states the negative performance impact of having a smaller LLC capacity is reduced. My proposed LLC architectures provide the same maximum performance and VDDMIN as the conventional architecture, while reducing the total LLC cell area by 15%-19% with negligible average runtime increase. Second, I present a technique supporting multiple voltage domains cost-effectively. This technique is based on the observations that (i) core-to-core voltages variations are relatively small when the voltages are optimized to maximize performance under a power constraint; (ii) per-core power-gating devices can be modified to serve as low-cost voltage regulators that can provide high efficiency in situations like (i) by augmenting them with small circuits; and (iii) core-to-core frequency/power variations are large due to within-die process variations. Our experimental results show that processors adopting our technique can achieve power efficiencies as high as ones using per-core on-chip switching voltage regulators with much less cost.