Technical Talks
NetApp E-Series and HPC Roadmap
Speaker: Robert Dilmore
Wednesday, March 19, 2014, 10:30-11:30 am
Visualization Lab, 346 Lewis Science Library
NetApp will be here to give an overview of their storage systems. We use these bricks in our GPFS implementation. The bricks allow for 60 disks in 4U with different RAID controllers having very different performance characteristics. Many other vendors OEM these products. It is certainly worth a listen if you ever need to add storage.
The Architecture for Discovery: HPC Insights from Intel®
Speaker: Tuong Nguyen, HPC Technical Specialist, Intel Corporation
Wednesday, February 5, 2014, 2:00 – 3:00 pm
Visualization Lab, 346 Lewis Science Library
Intel® is helping to blaze a path toward new innovation and discovery with its supercomputing vision and products. Please join us for insight into current and future HPC technologies, as Intel® looks forward to shaping this path with you.
This talk will focus on compute foundations for HPC – The Architecture of Discovery: Intel® Xeon® processors, Many Integrated Core architecture (Intel® MIC), and high-performance Fabric.
Exploiting Parallelism For Intel Xeon Processors & Phi Coprocessors
J.D. Patel and Jackson Marusarz, Intel Corporation
Thursday, January 30, 2014 ∙ 10:30 am - 1:00 pm
Thursday, January 30, 2014 ∙ 10:30 am - 1:00 pm
Visualization Lab ∙ 346 Lewis Science Library
(Lunch will be provided after the training.)
(Lunch will be provided after the training.)
Do you want to learn how to take advantage of highly parallel computation capabilities offered by Intel Xeon processors and Intel Xeon Phi coprocessors? Intel software development tools makes it easy to exploit parallel performance by using consistent parallel programming models and optimization techniques. Technical consulting engineers from Intel Corporation will be providing training on Intel software development tools:
Session 1 – Intel Compilers Optimizations & Phi Programming Models – J.D. Patel, Jayesh.Patel@intel.com
Rapidly growing parallelism offered by Intel multi-core processors and many-core coprocessors will be discussed, with emphasis on both thread & SIMD- level parallelization. Intel compilers’ easy to use optimization features such as vectorization, IPO, PGO, and Cilk Plus will be presented. Learn how to program Intel Xeon Phi Coprocessors, using different programming models – native, off-load, and symmetric. Both synchronous and asynchronous offload-modes will be discussed with examples.
Session 2 – Intel VTune Amplifier XE – Jackson Marusarz, Jackson.R.Marusarz@intel.com
Once you have running code, it’s time to optimize the performance. Intel® VTune Amplifier XE is a performance profiling tool that helps users visualize the performance of an application on Intel Xeon and Intel Xeon Phi co-processors. Learn how to profile an application to see where time is being spent, how well the hardware is being utilized, and discover bottlenecks that may hurt your performance. VTune Amplifier XE provides both command-line and GUI visualizations of performance data and can point out specific code regions that may be underperforming.
Get more performance with less effort!
HPC in the Multicore Era: Challenges and Opportunities
Speaker: David Barkai
HPC, Intel Corporation
Tuesday, September 21, 2010 1:00 pm - 2:00 pm Visualization Lab • 346 Lewis Science Library
Light refreshments served at 12:30 pm PICSciE reception area • 300 Lewis Science Library
Abstract
The application of "Moore's Law" still provides us with doubling the performance every generation through higher density of transistors on the chip, but also with the help of architectural innovation. What is a new phe-nomenon is that since the introduction of multicore the potential performance increase will not occur without assistance from the software and applications developers community. The challenges arise from the ever in-creasing level of concurrency, and the innovation required to maintain an adequate compute-bandwidth-latency balance. This talk will cover the current state of affairs in HPC, the hardware and software challenges, some approaches being studied to resolve them - new approaches to memory and IO systems, examination of more complex programming models (i.e., heterogeneous and hybrid); and the scientific discovery opportunities that will open up when those barriers are overcome.
Co-Sponsored by the Office of Information Technology (OIT)
