Engineering Quadrangle
F-Wing Room 216
Princeton, NJ 08540

Email: abhattac (at) princeton (dot) edu

Although I hail from the east Indian city of Kolkata, I have spent the overwhelming majority of my life elsewhere. Among other places, I have lived for extended periods of time in Italy, Malta, Canada, and USA.
Before my graduate studies at Princeton, I received a B.Eng in Honours Electrical Engineering from McGill University in August 2005. Prior to that, I completed my schooling from The Dwight School in Manhattan, New York in June 2001.
In my free time (according to an ugly rumour, this exists), I subject myself to the torture of supporting Arsenal, reading Wodehouse, and playing various racquet sports. I also use a Seagull S6 to create musical bedlam.

Research

My research interests broadly span the area of high-performance and low-power computer architecture. More specifically, my work addresses these themes for chip multiprocessors (CMPs).
Much of my dissertation work has focused on monitoring and exploiting the cache hierarchy to deduce runtime information on the speed at which threads of a parallel program execute. Based on this information, I have proposed modest microarchitectural support to use this data for dynamic performance and power management issues. In addition, I have studied the role of Translation Lookaside Buffers (TLBs) in CMP performance and have proposed mechanisms to augment traditional TLB hardware for performance benefits.
I have also done work on exploiting FPGA-based emulation to overcome the limits of software simulation in architecture research.

Publications

Abhishek Bhattacharjee, Gilberto Contreras, Margaret Martonosi, "Full-System Chip Multiprocessor Power Evaluations Using FPGA-Based Emulation", International Symposium on Low Power Electronics and Design (ISLPED-13), Aug. 2008.
(paper) (talk)
Acceptance Rate: 31%

Abhishek Bhattacharjee, Margaret Martonosi, "Thread Criticality Predictors for Dynamic Performance, Power, and Resource Management in Chip Multiprocessors", International Symposium on Computer Architecture (ISCA-36), June 2009.
(paper) (talk)
Acceptance Rate: 17%

Abhishek Bhattacharjee, Margaret Martonosi, "Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors", International Conference on Parallel Architectures and Compilation Techniques (PACT-18), Sept. 2009.
(paper) (talk)
Acceptance Rate: 18%
One of three finalists nominated for the Best Paper Award

Abhishek Bhattacharjee, Margaret Martonosi, "Inter-Core Cooperative TLB Prefetchers for Chip Multiprocessors", International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-15) , March 2010.
(paper) (talk)
Acceptance Rate: 17%

Work Experience

Through the course of my graduate studies, I have undertaken two internships at Intel to complement my dissertation research. Details are provided below:

Graduate Technical Intern, Strategic CAD Lab (June-Aug 2007)
Intel Corporation, Hudson, MA Supervisors: Emily Shriver, Michael Kishinevsky
My work focused on power modeling strategies for various interconnection network designs for future multicore processors. I worked on traffic-based models to estimate the power of various microarchitectural components of on-chip routers.

Graduate Technical Intern, VSSAD (June-Aug 2008)
Intel Corporation, Hudson, MA Supervisors: Michael Adler, Joel Emer
In accordance with my emulation interests, I worked on Hardware ASIM, a novel FPGA-based architectural performance modeling infrastructure with split timing and functional partitions. Specifically, I worked on the development of the cache hierarchy on the timing model side, specifying a uniform and complete interface for various cache modules and pipeline models.

Teaching

I have been an Assistant in Instruction (AI) for the following courses during my graduate studies:

Computer Architecture (ELE 475), Princeton University (Sept 2007 - Jan 2008)
Instructor: Prof. Margaret Martonosi
Course covers ISA design, high-performance microarchitecture, caches, multiprocessors, data and instruction-level parallelism, interconnection and network infrastructures.

Computer Architecture (COS/ELE 375), Princeton University (Sept 2009 - Jan 2010)
Instructor: Prof. Douglas Clark
Introduction to computer architecture and organization. Instruction set design, basic processor implementation techniques, performance measurement, caches and virtual memory, introduction to pipelining.

I have also mentored an undergraduate conducting independent research in our labs and was selected as one of two leaders for the Senior Thesis Writing Group in the Department of Electrical Engineering (Sept 2008 - May 2009). This initiative was undertaken by The McGraw Center for Teaching and Learning to provide guidance to junior and senior undergraduates conducting independent research projects. My role involved aiding them with the technical and presentation aspects of their research, thesis writing, and poster presentations.

Other Stuff

My research wordle is: