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Abhishek Bhattacharjee |
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Ph.D. Candidate Parapet Research Group Department of Electrical Engineering Princeton University
F218, Engineering Quadrangle Olden Street Princeton, NJ 08540
Email: abhattac (at) princeton (dot) edu
Updated CV (August 2008): (pdf)
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I am a fourth year doctoral student in the Department of Electrical Engineering at Princeton University. My advisor is Prof. Margaret Martonosi and I am a member of the Parapet Research Group.
My research interests lie in the area of high-performance and low-power computer architecture. My work addresses these themes on chip-multiprocessors with a view on developing microarchitectural support for various performance, power, and thermal issues. An intrinsic component of my work involves exploiting FPGA-based emulation to overcome the limitations of software simulators. In recognition of my work, I received Princeton's Wu Prize for Excellence in 2009, awarded to final-year engineering graduate students who have performed at the highest level as scholars and researchers.
While I hail from the east Indian city of Kolkata, I have mostly resided abroad in locations as varied as Canada, Italy, Malta, and the US.
I received my Masters degree from Princeton University in May 2007. Prior to that, I completed a B. Eng in Honours Electrical Engineering from McGill University in August 2005. I held the James McGill Scholarship during my four years there and was the recipient of the James McGill Award. I was also awarded the British Association Medal for Great Distinction upon graduation for having the highest rank in the Honours program. My undergraduate research focused on microelectromechanical (MEMS) resonators for radio-frequency transceivers. My advisor was Prof. Mourad El-Gamal and I carried out research for the RFIC Group.
Looking further back, I completed my schooling from The Dwight School in Manhattan, New York, where I was the class valedictorian. |
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Education |
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Ph.D. Candidate, Electrical Engineering Sept 2005 — Present M.A. Electrical Engineering (received in May 2007) Princeton University, Princeton, NJ
Advisor: Prof. Margaret Martonosi Selected Honours: First-year Graduate Fellowship, Wu Prize for Excellence Graduate Coursework: Advanced Computer Architecture, Switching and Sequential Systems, Linear System Theory, Photonics and Lightwave Communications, Low Power IC and System Design, Operating Systems, Parallel Programming and Architecture, Great Moments in Computing
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Research Interests |
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B.Eng, Honours Electrical Engineering Sept 2001 — Aug 2005 McGill University, Montreal, Quebec, Canada
Advisor: Prof. Mourad El-Gamal Selected Honours: James McGill Entrance Scholarship, James McGill Award, The British Association Medal for Great Distinction Graduate and Advanced Coursework: Computer Architecture, Microprocessor Systems, Digital Signal Processing, Radio-Frequency Microelectronics, Numerical Methods in EE, Semiconductor Devices
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International Baccalaureate Degree Sept 1999 — Sept 2001 The Dwight School, New York, NY Selected Honours: Class valedictorian, Wadham College award, American Chemical Society awards |
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Broadly speaking, my research focuses on investigating microarchitectural techniques to improve performance and mitigate power and thermal characteristics of novel multicore architectures. In order to conduct effective analysis of the performance and power implications of a proposed design, I have been tackling the various problems posed by architectural software simulators today. In response to credibility issues arising from long simulation times, I have been investigating FPGA-based hardware acceleration techniques to accommodate performance and power modeling.
The following publication describes my initial foray in the area of FPGA-based emulation.
Abhishek Bhattacharjee, Gilberto Contreras, Margaret Martonosi, “Full-System Chip Multiprocessor Power Evaluations Using FPGA-Based Emulation”, International Symposium on Low Power Electronics and Design (ISLPED), August 2008 (paper) (talk) I have also worked on hardware detection mechanisms to identify the slowest or critical threads of parallel programs on CMPs. The prediction strategies and their uses are detailed in:
Abhishek Bhattacharjee, Margaret Martonosi, “Thread Criticality Predictors for Dynamic Performance, Power, and Resource Management in Chip Multiprocessors”, International Symposium on Computer Architecture (ISCA-36), June 2009 (paper) (talk) Following from the thread criticality prediction work, I am also interested in studying mechanisms to accelerate critical threads. Specifically, I have studied the potential of exploiting inter-core TLB miss patterns to speed critical threads. An initial characterization of TLB behavior of CMPs is provided in:
Abhishek Bhattacharjee, Margaret Martonosi, “Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors”, International Conference on Parallel Architectures and Compilation Techniques (PACT-18), Sept 2009. (One of three finalists selected for the Best Paper Award) (paper) (talk)
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Internships |
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To complement my research interests, I have pursued a couple of enriching internships with Intel Corporation. Details of my contributions are listed below.
Graduate Technical Intern, VSSAD June 2008 — Aug 2008 Intel Corporation, Hudson, MA
Supervisors: Dr. Michael Adler, Dr. Joel Emer Research: In accordance with my hardware emulation interests, I concentrated on the development of Hardware ASIM, a novel FPGA-based architectural performance modeling infrastructure with split functional and timing partitions. Specifically, I addressed the development of the cache hierarchy on the timing model side. This involved specifying the requisite interfaces and formulating the caches into appropriate modules. I will be collaborating on the development of HASIM beyond the internship and will be using the infrastructure for future cache studies. An overview of HAsim with details of my work included may be seen at the following:
Joel Emer, Michael Adler, Angshuman Parashar, Michael Pellauer, Murali Vijayraghavan, Nikhil Patil, Abhishek Bhattacharjee, HAsim Update at RAMP Retreat, August 2008
Graduate Technical Intern, Strategic CAD Labs June 2007 — Aug 2007 Intel Corporation, Hudson, MA
Supervisors: Dr. Emily Shriver, Dr. Michael Kishinevsky Research: My work in SCL dealt with the power modeling of interconnection networks in future Intel multicore designs. Traffic-based models were implemented to estimate power for various components of the router microarchitecture. To accurately simulate our power estimation techniques, I refined the ASIM simulator to include power modeling capabilities for general purpose modules.
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Teaching |
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I was an Assistant in Instruction for ELE 475 — Computer Architecture in the Fall of 2007. This course introduces advanced elements of superscalar and VLIW pipelines, memory hierarchies, multiprocessors, interconnection networks, and other computer systems topics. The class is catered to final year undergraduates and first year graduate students. My responsibilities involved grading assignments, aiding in the construction and grading of exams, as well as taking charge of the infrastructure for the course project. The latter involved various memory hierarchy studies using the Multifacet GEMS simulator.
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Brief Bio |
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I have been a reviewer for ISCA 2008 and PACT 2008.
I am a member of the Association for Computing Machinery (ACM) and the Gigascale Systems Research Center (GSRC). I have also co-founded the Computer Architecture Reading Group (CARG) at Princeton for students in the Departments of Electrical Engineering and Computer Science.
In my spare time, I enjoy racquet sports and soccer, play the guitar and read Wodehouse. |
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Other Activities |