IBM 1620 Model II

related topics
{system, computer, user}
{math, number, function}

The IBM 1620 Model II (commonly called simply the Model II) was a vastly improved implementation, compared to the original Model I, of the IBM 1620 scientific computer architecture.

It had basic ALU hardware for addition and subtraction, but multiplication was still done by table lookup in core memory. Multiplication used a 200 digit table (@ address 00100..00299). Rather than being an available option, as in the Model I, the divide hardware using a repeated subtraction algorithm, was built in. Floating point arithmetic was an available option, as were octal input/output, logical operations, and base conversion to/from decimal instructions.

The core memory (@ address 00300..00399) that was freed by the replacement of the addition table with hardware was used for storage of two selectable "bands" of seven 5-digit index registers.

The console typewriter was replaced with a modified Selectric typewriter, which could type at 15.5 cps — a 55% improvement over the Model I.

The entire core memory was in the IBM 1625 memory unit. Memory cycle time was halved compared to the Model I's (internal or 1623 memory unit), to 10 µs (i.e., the cycle speed was raised to 100 kHz) by using faster cores. A Memory Address Register Storage (MARS) core memory read, clear, or write operation took 1.5 µs and each write operation was automatically (but not necessarily immediately) preceded by a read or clear operation of the same "register(s)" during the 10 µs memory cycle.

The processor clock speed was also doubled, to 2 MHz, which was still divided by 20 by a 10 position ring counter to provide the system timing/control signals.

The fetch/execute mechanism was completely redesigned, optimizing the timing and allowing partial fetches when the P or Q fields were not needed. Instructions took either 1, 4, or 6 Memory cycles (10 µs, 40 µs, or 60 µs) to fetch and a variable number of memory cycles to execute. Indirect addressing added 3 memory cycles (30 µs) for each level of indirection. Indexed addressing added 5 memory cycles (50 µs) for each level of indexing. Indirect and indexed addressing could be combined at any level of indirection or indexing.

Contents

Non-decimal arithmetic

Unlike the Model I addition and subtraction were now fully implemented in hardware, so changing the table in memory could not be used as a "trick" to change arithmetic bases. However an optional special feature in hardware for octal input/output, logical operations, and base conversion to/from decimal was available. This made the Model II very practical for applications that needed to manipulate data formatted in octal by other computers (e.g., the IBM 7090).

Bases other than 8 and 10 were not supported.

Operating procedures

Upper console

Full article ▸

related documents
QuickBASIC
Electrical network
Source Mage GNU/Linux
Wireless Markup Language
Video coding
Simple DirectMedia Layer
Segmentation fault
Allegro library
Revision Control System
Java Platform, Enterprise Edition
Computing platform
Berkeley DB
Modifier key
System request
Corel Ventura
Multiple-image Network Graphics
Konqueror
Samba (software)
GTK+
Red Hat Linux
Coda (file system)
Macro virus (computing)
Abstract Window Toolkit
Floating point unit
Core dump
HTTP 404
Turbo Pascal
Batch processing
XEmacs
Sendmail