MMX (instruction set)

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MMX is a single instruction, multiple data (SIMD) instruction set designed by Intel, introduced in 1996 with their P5-based Pentium line of microprocessors, designated as "Pentium with MMX Technology".[1][2] It developed out of a similar unit first introduced on the Intel i860. MMX is a processor supplementary capability that is supported on recent IA-32 processors by Intel and other vendors.

Intel's competitor AMD enhanced Intel's MMX with the 3DNow! instruction set to work with floating-point numbers. Intel would follow AMD's lead on floating-point math and created the SSE extension a year after 3DNow! was introduced.

Contents

Naming

MMX is officially a meaningless initialism trademarked by Intel[citation needed]; unofficially, the initials have been variously explained as standing for MultiMedia eXtension, Multiple Math eXtension, or Matrix Math eXtension.

AMD, during one of its numerous court battles with Intel, produced marketing material from Intel indicating that MMX stood for "Matrix Math Extensions". The idea that it stands for nothing is an Intel corporate position meant to suggest that it is of trademarked status and cannot be used by AMD or other x86 clone manufacturers in their own marketing material.[3]

Technical details

MMX defined eight registers, known as MM0 through MM7 (henceforth referred to as MMn). To avoid compatibility problems with the context switch mechanisms in existing operating systems, these registers were aliases for the existing x87 FPU stack registers (so no new registers needed to be saved or restored). Hence, anything that was done to the floating point stack would also affect the MMX registers and vice versa. However, unlike the FP stack, the MMn registers are directly addressable (random access).

Each of the MMn registers holds 64 bits (the mantissa-part of a full 80-bit FPU register). The main usage of the MMX instruction set is based on the concept of packed data types, which means that instead of using the whole register for a single 64-bit integer, two 32-bit integers, four 16-bit integers, or eight 8-bit integers may be processed concurrently.

The mapping of the MMX registers onto the existing FPU registers made it somewhat difficult to work with floating point and SIMD data in the same application. To maximize performance, programmers often used the processor exclusively in one mode or the other, deferring the relatively slow switch between them as long as possible.

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