Motorola 68020

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The Motorola 68020 is a 32-bit microprocessor from Motorola, released in 1984. It is the successor to the Motorola 68010 and is succeeded by the Motorola 68030. A lower cost version was also made available, known as the 68EC020.



The 68020 (usually just referred to as the '020, pronounced oh-two-oh or oh-twenty) had 32-bit internal and external data and address buses. The 68EC020 only had a 24-bit address bus. The 68020 was produced at speeds ranging from 12 MHz to 33 MHz.

Improvements over 68010

The 68020 added many improvements to the 68010 including a 32-bit arithmetic logic unit (ALU), external data bus and address bus, and new instructions and addressing modes. The 68020 (and 68030) had a proper three-stage pipeline. Though 68010 had a loop mode, it was little used. The 68020 replaced this with a proper instruction cache of 256 bytes, the first 68k series processor to feature proper onboard cache memory.

The previous 68000 and 68010 processors could only access word (16 bit) and longword (32 bit) data if it were word-aligned (located at an address that is evenly divisible by 2). The 68020 had no alignment restrictions on data access. However, unaligned longword accesses were often much slower than aligned accesses.

Coprocessor support

The MC68020 has a coprocessor interface supporting up to eight coprocessors. The main CPU recognizes "F-line" instructions (with the four most significant opcode bits all one), and uses special bus cycles to interact with a coprocessor to execute these instructions. Two types of coprocessors were defined, the floating point unit (MC68881 or MC68882 FPU) and the paged memory management unit (MC68851 PMMU). Only one PMMU can be used with a CPU. In principle multiple FPUs could be used with a CPU, but it was not commonly done. The coprocessor interface is asynchronous, so it is possible to run the coprocessors at a different clock rate than the CPU.

Multiprocessing features

Multiprocessing support was implemented externally by the use of a RMC pin[1] to indicate an indivisible read-modify-write cycle in progress. All other processors had to hold off memory accesses until the cycle was complete.[2] Software support for multiprocessing included the TAS, CAS and CAS2 instructions.

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