Motorola 6809

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The Motorola 6809 is an 8-bit (with some 16-bit features) microprocessor CPU from Motorola, introduced circa 1977-78. It was a major advance over both its predecessor, the Motorola 6800, and the related MOS Technology 6502.

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Among the significant enhancements introduced in the 6809 were the use of two 8-bit accumulators (A and B, which could be combined into a single 16-bit register, D), two 16-bit index registers (X, Y) and two 16-bit stack pointers. The index and stack registers allowed very advanced addressing modes. Program counter relative addressing allowed for the easy creation of position-independent code, while a user stack pointer (U) facilitated the creation of reentrant code.

The 6809 was source-compatible with the 6800, though the 6800 had 78 instructions to the 6809's 59. Some instructions were replaced by more general ones which the assembler translated into equivalent operations and some were even replaced by addressing modes. The instruction set and register complement were highly orthogonal, making the 6809 easier to program than the 6800 or 6502.

Other features were one of the first hardware-implementations of a multiplication instruction in an MPU, full 16-bit arithmetic and an especially fast interrupt system. The 6809 was also highly optimized, up to five times faster than the 6800 series CPUs. Like the 6800, it included an undocumented address bus test instruction that would exceed the limits of some memory controllers, evoking the nickname Halt and Catch Fire (HCF)[citation needed].

The 6809's state machine and control logic, unlike many processors of the day, was mostly implemented using a large PLA and asynchronous random logic (a trait of early designs and, partly, of RISC) rather than microcoded. The 6809 used the two-phase clock cycle directly as the basic machine cycle.

Although this means fewer clock cycles per instruction compared to the Z80 for instance, the latter's higher resolution state machine allowed clock frequencies 3-5 times as high without demanding faster memory chips, which was often the limiting factor. This is because the Z80 combines two full (but short) clock cycles into a relatively long memory access period compared to the clock, while the more asynchronous 6809 instead has relatively short memory access times: depending on version and speed grade, approximately 60% of a single clock cycle was typically available for memory access in a 6809 (see data sheets).

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