Motorola 88000

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The 88000 (m88k for short) is a RISC instruction set architecture (ISA) developed by Motorola. The 88000 was Motorola's attempt at a home-grown RISC architecture, started in the 1980s. Having arrived some two years after its competition, in the form of the SPARC and MIPS, the 88000 never managed to catch on.

Though sometimes referred to as A88k, the Apollo PRISM is not related to the Motorola 88000.[1]



Originally called the 78000 as a homage to their famed 68000 series, the design went through a tortured development path, including the name change, before finally emerging in April 1988.

In the late 1980s several companies were actively watching the 88000 for future use, including NeXT, Apple Computer and Apollo Computer, but all gave up by the time the 88110 was available in 1990.

There was an attempt to popularize the system with the 88open group, similar to what Sun Microsystems was attempting with their SPARC design. It appears to have failed in any practical sense.[2]

In the early 1990s Motorola joined the AIM effort to create a new RISC design based on the IBM POWER design. They worked a few features of the 88000 into the new PowerPC design to offer their customer base some sort of upgrade path. At that point the 88000 was dumped as soon as possible.[3]


Like the 68000 before it, the 88000 was considered to be a very "clean" design. It was a pure 32-bit load/store architecture, using separate instruction and data caches (Harvard architecture), and separate data and address buses. It had a small but powerful command set, and, like all Motorola CPUs, did not use memory segmentation.

A major architectural mistake was that both integer instructions and floating-point instructions used the same register file. This required the single register file to have sufficient read and write ports to support both the integer execution unit and the floating-point unit. The connections for each port is an additional capacitive load that must be driven by register memory cell. This made it more difficult to build high frequency superscalar implementations.[citation needed]

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