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SPARC (from Scalable Processor Architecture) is a RISC instruction set architecture (ISA) developed by Sun Microsystems and introduced in mid-1987.

SPARC is a registered trademark of SPARC International, Inc., an organization established in 1989 to promote the SPARC architecture, manage SPARC trademarks, and provide conformance testing. Implementations of the original 32-bit SPARC architecture were initially designed and used in Sun's Sun-4 workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68000 family of processors. Later, SPARC processors were used in SMP servers produced by Sun Microsystems, Solbourne and Fujitsu, among others, and designed for 64-bit operation.

SPARC International was intended to open the SPARC architecture to make a larger ecosystem for the design, which has been licensed to several manufacturers, including Texas Instruments, Atmel, Cypress Semiconductor, and Fujitsu. As a result of SPARC International, the SPARC architecture is fully open and non-proprietary.

In March 2006, the complete design of Sun Microsystems' UltraSPARC T1 microprocessor was released-in open-source form at and named the OpenSPARC T1. In 2007, the design of Sun's UltraSPARC T2 microprocessor was also released in open-source form, as OpenSPARC T2; see

As of June 2009 the SPARC design was used by Fujitsu Laboratories Ltd. to create the processor product named Venus SPARC64 VIIIfx which is capable of 128 billion floating point operations per second (128 GFLOPs).



The SPARC architecture was heavily influenced by the earlier RISC designs including the RISC I and II from the University of California, Berkeley and the IBM 801. These original RISC designs were minimalist, including as few features or op-codes as possible and aiming to execute instructions at a rate of almost one instruction per clock cycle. This made them similar to the MIPS architecture in many ways, including the lack of instructions such as multiply or divide. Another feature of SPARC influenced by this early RISC movement is the branch delay slot.

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