SuperH (or SH) is a 32-bit reduced instruction set computer (RISC) instruction set architecture (ISA) developed by Hitachi. It is implemented by microcontrollers and microprocessors for embedded systems.
The SuperH processor core family was first developed by Hitachi in the early 1990s. Hitachi has developed a complete group of upward compatible instruction set CPU cores. The SH-1 and the SH-2 were used in the Sega Saturn and Sega 32X. These cores have 16-bit instructions for better code density than 32-bit instructions, a benefit at the time as memory was very expensive.
A few years later the SH-3 core was added to the SH CPU family; new features included another interrupt concept, a memory management unit (MMU) and a modified cache concept. The SH-3 core also got a DSP extension, then called SH-3-DSP. With extended data paths for efficient DSP processing, special accumulators and a dedicated MAC-type DSP engine, this core was unifying the DSP and the RISC processor world. A derivative was also used with the original SH-2 core.
For the Dreamcast, Hitachi developed the SH-4 architecture. Superscalar (2-way) instruction execution and a vector floating point unit were the highlights of this architecture. SH-4 based standard chips were introduced around 1998.
In early 2001, Hitachi and ST Microelectronics formed the IP company SuperH, Inc., which was going to license the SH-4 core to other companies and was developing the SH-5 architecture, the first move of SuperH into the 64-bit area. SuperH, Inc. sold the IP of these CPU cores to Renesas Technology in 2004.
The SH-5 design supported two modes of operation. SHcompact mode is equivalent to the user-mode instructions of the SH-4 instruction set. SHmedia mode is very different, using 32-bit instructions with sixty-four 64-bit integer registers and SIMD instructions. In SHmedia mode the destination of a branch (jump) is loaded into a branch register separately from the actual branch instruction. This allows the processor to prefetch instructions for a branch without having to snoop the instruction stream. The combination of a compact 16-bit instruction encoding with a more powerful 32-bit instruction encoding is not unique to SH-5; recent ARM processors have a 16-bit Thumb mode, and MIPS processors have a MIPS-16 mode. However, SH-5 differs because its backward compatibility mode is the 16-bit encoding rather than the 32-bit encoding.
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