•  T1: Innovating with OpenSPARC

• Time: Saturday Oct 21, 9:00am-12:15pm
• Organizers:  David Weaver and Shrenik Mehta, Sun Microsystems Inc.
• Abstract: OpenSPARC T1 is the world's first 64-bit, 32-thread, open-source hardware design -- freely available under the GNU Public License (GPL).   It provides an unprecedented research vehicle and a highly-threaded, reconfigurable microprocessor design from which custom variants can quickly be designed.   With today's complex microprocessors taking years of elapsed time and tens to hundreds of millions of dollars to develop, OpenSPARC T1 provides a starting point that allows developers and researchers to stand on the shoulders of a proven, verified, high-performance design, shortening time-to-market, and dramatically lowering development costs.
  
  This tutorial will provide the background for building systems and software using the OpenSPARC design.  Members of the OpenSPARC T1 development team will present an introduction to OpenSPARC T1, including:

• Overview of OpenSPARC processor architecture (changes since SPARC V9) and OpenSPARC T1 microarchitecture (processor organization, pipeline, threading model)
• SAM-T1 simulation tools for OpenSPARC (architecture model, full-system simulation platform, device models, device driver development, trace generation, user interface, etc)
• Virtualization on OpenSPARC: Porting /your/ operating system on top of the Hypervisor
• Maximizing the benefits of CMT with CoolTool development tools (compilers, GCC, etc)
• Creating optimal SPARC executables using the Automated Tuning System (ATS)

An overview of OpenSPARC T1 can be found at http://OpenSPARC.net .

• T2: A Deep-Submicron CMOS Primer
• Time: Saturday Oct 21, 2:pm-5:00pm
• Organizers:  J. Adam Butts, IBM T.J. Watson Research Center
• Abstract: This tutorial will survey the physical implementation of CMOS circuitry with particular attention to the constraints and non-idealitites of the sub-100nm regime.  Topics will include transistor and interconnect scaling, leakage mechanisms, power dissipation, reliability, variability, and yield.  As the influence of these issues on circuit design increases, their effects must be accounted for earlier in the design process.  The rising prevalence of some of these topics at ASPLOS illustrates this point.  This tutorial will explain the origins of these trends in the technology and connect them with their architectural consequences, allowing participants to better participate in the new research directions that are arising as a result.

• T3: Enterprise Power and Cooling: A Chip-to-Data-Center Perspective
• Time: Sunday Oct 22, 8:30am-12:00pm
• Organizers:
• Chandrakant D. Patel, Hewlett Packard Labs
• Parthasarathy Ranganathan, Hewlett Packard Labs
• Abstract: Power and cooling are increasingly becoming key challenges in enterprise environments, impacting infrastructure, electricity, and maintenance costs, as well as compaction, reliability, and environmental standards’ compliance. In the future, it is going to be important to address these challenges “holistically” – across the different levels of the hardware and software stacks while considering the total cost of ownership (TCO). For example, power and cooling need to be considered together along with performance and reliability, as decisions made for one influence the choices and costs for the other. Similarly, there is a need for cross-cutting solutions going beyond better adaptivity in the system elements to include the operating system and the management and applications software stack. Co-ordination is also needed across the entire “ensemble” – from chips to data centers. All this will require interdisciplinary research spanning electrical engineering, computer science, and thermal science. In aid of this, our tutorial seeks to provide a broad overview of the power and cooling problem in enterprises. We present recent industry trends to motivate the problem and then discuss current cooling and power work in the context of a unified framework from chip-core to data center. We conclude with a discussion of holistic optimizations for the problem including a detailed case study of the HP Labs Smart Data Center.

• T4: Using Systemsim to Guide Application Transformation and Tuning for the Cell Broadband Engine
• Time: Sunday Oct 22, 1:30pm-5:00pm
• Organizers:
• Patrick Bohrer
• Vipin Sachdeva
• Mike Kistler
• Jim Peterson
• Dave Murrell, all IBM
• The Cell Broadband Engine SDK embodies a programming environment featuring an assortment of mechanisms to accelerate application performance. Parallel programming constructs, vector SIMD operations, and DMA scatter/gather capabilities are all supported by this freely available IBM Alphaworks offering (http://www.alphaworks.ibm.com/tech/cellsw). In order to take full advantage of the CBE platform performance potential, cell software developers typically need to re-structure their applications to incorporate the SDK programming paradigms. The Systemsim Cell simulator furnishes an array of instrumentation and displays that are valuable for gaining insight into application characteristics and system behavior.
  
  The focus of this tutorial is to introduce Systemsim performance analysis features used to guide the process of converting a scalar application into a parallel SIMD version controlled by the PPE and accelerated by SPEs. A demonstration of this process will be given for a sample vectorizable application. At each step along the transformation, we will present Systemsim measurement capture and visualization facilities, and explain how to interpret the resulting data to guide trade-off decisions. Some techniques and tools which assist in balancing computation with DMA data movement will also be introduced.
  
  Although the tutorial will include a brief overview of the CBE architecture and the SDK components, exposure to the Cell Broadband Engine architecture and familiarity with the SDK sufficient to compile and run applications on Systemsim is assumed.

• T5: Intel Virtualization Technology (VT): Motivation and Architecture
• Time: Sunday Oct 22, 1:30pm-5:00pm
• Organizers:
• Richard Uhlig, Intel
• Gil Neiger, Intel
• Abstract: In this tutorial we examine aspects of the IA-32 instruction-set architecture (ISA) that complicate the implementation of virtual machine monitors (VMMs) for Intel-based platforms.  We then introduce Intel VT, an extension to the IA-32 system ISA that addresses these challenges, and simplifies the design of IA-32 VMMs.  The tutorial will include a detailed overview of the various architectural features of VT, and explain how they can be used to build a VMM for IA-based systems.