*
* Command Line:      ../test -A -d elliptic.dfg -f 1.2 -t 1 -l cbc9vx.libr
sample period =0
*
*  Reading CDFG from file "elliptic.dfg"
*
*
*  Reading LIBRARY from file "cbc9vx.libr"
ERROR: Line 70: Bad character/keyword/identifier
ERROR: Line 92: Bad character/keyword/identifier
*
Wire scale 1 Gate scale 1 Lamda scale 1
*  BEGIN LEVELIZING DFG...
*  END LEVELIZING DFG...
*
*  BEGIN SC_SIMULATION...
*

*
*  END SC_SIMULATION...
*
*  ATTEMPTING AREA OPTIMIZATION...
sample_constraint = 0
laxity = 1.2
Set the sample_period as the 1.2 times fastest_sample_period 160
*
max csteps = 14 min csteps = 5
Iterative improvement synthesis No.: 1, Vdd: 5, Contol Steps: 14
Fully parallel result: 
Datapath::do_floorplan()  FU # = 33 Reg # = 52 Mux # = 118
 Datapath area efficiency: 0.609326 Total datapath area is 158582
Iterative improvement synthesis No.: 2, Vdd: 5, Contol Steps: 13
Fully parallel result: 
Datapath::do_floorplan()  FU # = 33 Reg # = 52 Mux # = 118
 Datapath area efficiency: 0.609326 Total datapath area is 158582
Iterative improvement synthesis No.: 3, Vdd: 5, Contol Steps: 12
Fully parallel result: 
Datapath::do_floorplan()  FU # = 33 Reg # = 52 Mux # = 118
 Datapath area efficiency: 0.609326 Total datapath area is 158582
OOPS - cannot meet sample period with Vdd: 5 control steps:11 best csteps possible: 12
OOPS - cannot meet sample period with Vdd: 5 control steps:10 best csteps possible: 12
Iterative improvement synthesis No.: 4, Vdd: 5, Contol Steps: 9
Fully parallel result: 
Datapath::do_floorplan()  FU # = 33 Reg # = 52 Mux # = 118
 Datapath area efficiency: 0.609326 Total datapath area is 158582
Iterative improvement synthesis No.: 5, Vdd: 5, Contol Steps: 8
Fully parallel result: 
Datapath::do_floorplan()  FU # = 33 Reg # = 52 Mux # = 118
 Datapath area efficiency: 0.609326 Total datapath area is 158582
Iterative improvement synthesis No.: 6, Vdd: 5, Contol Steps: 7
Fully parallel result: 
Datapath::do_floorplan()  FU # = 33 Reg # = 52 Mux # = 118
 Datapath area efficiency: 0.609326 Total datapath area is 158582
OOPS - cannot meet sample period with Vdd: 5 control steps:6 best csteps possible: 7
OOPS - cannot meet sample period with Vdd: 5 control steps:5 best csteps possible: 7
*  END AREA OPTIMIZATION
Best solution at Vdd: 5 sample period: 192 control steps: 8
Final after floorplanning: 
Note: the VDD of the lib energy data is not known. Assumed 1 V
Datapath::do_floorplan()  FU # = 12 Reg # = 20 Mux # = 44
 Datapath area efficiency: 0.66652 Total datapath area is 59551.9
Datapath::compute_sccost()  Logic Energy in pJoule = 393.935  Wire Energy in pJoule = 65.0927  Mux Energy in pJoule = 43.0617
 TOTAL = 502.089
 Gated num = 86 Switching num = 95
 Gating overhead energy 13.2761 area  222.912
 wire energy computed by output network is 43.078
 wire energy of shared wire is 43.5616 reduced is 27.3985
 NC = 3.46433
Total Power = 2.61505
Total Energy = 502.089
Wire energy is 65.0927
Mux energy is 43.0617
Logic energy is 393.935
Reduced module sc is 133.909
Reduced wire energy is 23.6322
Shared wire energy would be 43.5616reduced is 27.3985
MST wire energy would be 43.078
Reduced mux energy is 14.3388
