Computer Engineering

Previous Students

“I'm an assistant professor now. Check my webpage for more information.”

“Compiler Optimizations for High-Performance Computing, Program Analysis to exploit memory hierarchy, High-level Synthesis of VLSI circuits.”

“Developing CAD tools that target low-power designs of conditional, loop, and memory intensive circuits.”

“Computer-aided design of computer system and integrated circuits, with special interests in Hardware/Software codesign, Scheduling techniques for hetergeneous multi-processor machines, Multimedia, HML -- An innocative hardware description language (HDL).”

“The execution time of a program may vary significantly according to different input data and initial system states. In many cases, e.g. real-time systems, it is important to determine the worst case execution time of the program. My research interest is in determining a tight estimate on this worst case execution time.”

“Electronic Design Automation for Digital VLSI systems, focusing on Analysis and optimization of power consumption at all levels of the design hierarchy and Testing -- Automatic test generation, design-for-test and synthesis-for-testability.”

“My thesis research focuses on allocation, scheduling and co-synthesis of distributed hard, real-time systems. Recently, I have been looking at what I call `data arrival design' which entails deciding how data transmitted in a task-dag should appear to the processing element (e.g. should it use an interrupt). I am now broadening this work to a full co-synthesis level, able to design systems with cost as a goal using as input the work that Robert Dick and I did, TGFF. As a full time employee, I also am involved in many other things, please see my web page for more.”

“My research focuses on retargetable compilation for embedded DSP processors.”

“The focus of my current research is on issues related to power consumption in digital systems. It involves the development of new tools and techniques for power estimation and low power design at different levels of the design process.”