Carole-Jean Wu

Engineering Quad.
Olden Street
Princeton University
Princeton, NJ 08540

Email: carolewu [at] princeton edu
Phone: (607) 592-6397

I am third-year Ph.D. student in the Department of Electrical Engineering at Princeton University. My advisor is Margaret Martonosi, and I am a member of the Parapet Research Group.

My research interests focus on shared resource management for CMP systems. In particular, I investigate hardware techniques in various granularity levels that assist the management of the last-level shared CMP caches, targeting at performance throughput and quality of service. I am also interested in techniques that exploit potential parallelism hidden in multi-threaded applications on CMP systems. I have looked into both transactional memory works, as well as data-centric synchronization approaches, that grant granularity levels other than simply coarse- or fine-grained parallelism.

Currently I lead the Computer Architecture Reading Group (CARG) in the Departments of Electrical Engineering and Computer Science at Princeton University.

I graduated from School of Electrical and Computer Engineering at Cornell University in 2006, where I worked with Jose Martinez.
 
My resume can be found here.

Education

  • Princeton University, School of Engineering and Applied Science, Princeton, NJ [9/2006 – present]
      3rd-year Ph.D. Candidate in Electrical Engineering
      M.A. in Electrical Engineering (received in 5/2008)

  • Cornell University, College of Engineering, Ithaca, NY [9/2002 – 5/2006]
      B.S. in Electrical and Computer Engineering
      Dean’s List: 2003 2004 2005
      Cum Laude Honors

Publication

Research Talks

Work Experience

  • Graduate Technical Intern @ CTG-STL-PSL, Intel Corporation [6/2008 – 8/2008]

      Analyze performance and scalability issues related to System Management mode (SMM) on Intel's many-core and Tera-scale platforms.

  • IBM Research Intern @ TJ Waston Research Lab [6/2007 – 8/2007]


  • Technical Intern @ SSG-AET-ATP, Intel Corporation [5/2005 – 8/2005]

      Profiled and characterized threading behaviors of various applications using Intel ThreadTracker, Thread Profiler and VTune performance analyzer.
      Generated multi-threaded traces for IA32 pre-Si simulations for various applications, validated traces were representative, and performed pre-Si architectural analysis.

  • Technical Intern @ SSG-AET-ATP, Intel Corporation [8/2004 – 12/2004]

      Built RT viewer, a graphical tool, that characterizes threading behavior of an application in the pre-Si environment in a multi-core/multi-processor system (using C++).
      Debugged a media decoder for Microsoft and analyzed performance using Intel VTune performance analyzer.

Tools

  • I use GEMS, a full system simulator, on top of SIMICS, a functional processor model, , as a toolset to evaluate my architectural proposals.

Courses