Carole-Jean Wu

Engineering Quad.
Olden Street
Princeton University
Princeton, NJ 08540

Email: carolewu [at] princeton [dot] edu
Phone: (607) 592-6397

Announcement

I am looking for strong and motivated students who are interested in Computer Architecture and System Designs.

Exciting News

  • May 1, 2012

    I am featured on the Spring 2012 issue of the CRA-W Newsletter!

  • April 26, 2012

    I will be joining the faculty of Ira A. Fulton Schools of Engineering in Arizona State University as an Assistant Professor. My appointment at the School of Computing, Informatics, and Decision Systems Engineering will begin in August, 2012.

  • April 16, 2012

    I successfully defended my PhD dissertation: Dynamic Techniques for Mitigating Inter- and Intra-Application Cache Interference. A copy of my PhD thesis can be downloaded from here.

  • Older news archived here.

About Me

I obtained my Ph.D. degree in the Department of Electrical Engineering at Princeton University under the supervision of Professor Margaret Martonosi.

My research interests focus on shared resource management for Chip-Multiprocessor (CMP) systems. In particular, I investigate hardware techniques at various granularity levels to assist in the management of the last-level shared CMP caches, targeting performance throughput and quality of service. I am also interested in techniques that exploit potential parallelism hidden in multi-threaded applications on CMP systems. I have looked into transactional memory as well as data-centric synchronization approaches to explore potential thread-level parallelism in modern workloads.

I led the Computer Architecture Reading Group (CARG) in the Departments of Electrical Engineering and Computer Science at Princeton University from 2007 to 2009. Computer Architecture Day at Princeton 2009 organized by us was a splendid success [See photos].

I graduated from the School of Electrical and Computer Engineering at Cornell University in 2006 where I worked with Professor Jose Martinez. My undergraduate thesis is on the predictability of microprocessor LLC miss values.
 
My resume can be found here.

Education

  • Princeton University, School of Engineering and Applied Science, Princeton, NJ [9/2006 – 4/2012]
      Ph.D. in Electrical Engineering
      M.A. in Electrical Engineering (received in 5/2008)

  • Cornell University, College of Engineering, Ithaca, NY [9/2002 – 5/2006]
      B.S. in Electrical and Computer Engineering
      Dean’s List: 2003 2004 2005
      Cum Laude Honors

Honor/Award

  • Intel Graduate Fellowship 2011
  • Excellence in Leadership Award (Computer Architecture Day @ Princeton 2009)
  • Princeton First-Year Graduate Fellowship
  • Undergraduate Research Funding from Intel (CURB)
  • Best COOP Student of Year 2005 from Cornell and Intel

Publication

Research Talks

Other Talks

  • Building Self Confidence.

      Presented with Prof. Mary Jane Irwin (Penn State University) in Computing Research Association for Women (CRA-W) GradCohort '09

Teaching Experience

  • Assistant in Instruction [1/2009 – 5/2009]

      TAed for ELE391 Wireless Revolution: Telecommunications for the 21st Century taught by Professor Sanjeev Kulkarni.

  • Academic Excellence Workshop Facilitator [8/2003 – 12/2005]

      Led enrichment workshops for calculus classes and promoted group learning for better understanding of course materials.

  • Teaching Assistant for Pre-freshman Program [6/2004 – 8/2004]

      Prepared undergraduate Calculus lesson plans and facilitated discussion/office hours.

Work Experience

  • Graduate Technical Intern @ IAG-CAP-VSSAD, Intel Corporation [9/2010 – 5/2011]

      Proposed instruction-level, signature-based cache hit predictors to guide cache replacement.

      Designed novel high performing memory management techniques to improve cache utilization for multimedia, games, enterprise servers, and scientific workloads.

  • Engineering Intern @ Platform Software Development, Google Inc. [6/2009 – 8/2009]

      Developed a portfolio of application-level power prediction algorithms for Google data centers. This portfolio includes machine learning algorithms and linear regression techniques that exploit application CPU/power utilization history as well as algorithms that simply react to demand.

      Analyzed Google benchmark and random CPU utilization traces sampled in production environment. Evaluated the effectiveness in prediction accuracy and the usability of the studied algorithms for representative workloads.

  • Graduate Technical Intern @ CTG-STL-PSL, Intel Corporation [6/2008 – 8/2008]

      Analyzed performance and scalability issues related to System Management mode (SMM) on Intel's many-core and Tera-scale platforms.

  • Research Intern @ IBM TJ Waston Research Lab [6/2007 – 8/2007]


  • Technical Intern @ SSG-AET-ATP, Intel Corporation [5/2005 – 8/2005]

      Profiled and characterized threading behaviors of various applications using Intel ThreadTracker, Thread Profiler and VTune performance analyzer.

      Generated multi-threaded traces for IA32 pre-Si simulations for various applications, validated traces were representative, and performed pre-Si architectural analysis.

  • Technical Intern @ SSG-AET-ATP, Intel Corporation [8/2004 – 12/2004]

      Built RT viewer, a graphical tool that characterizes threading behavior of an application in the pre-Si environment in a multi-core/multi-processor system.

      Debugged a media decoder for Microsoft and analyzed performance using Intel VTune performance analyzer.

Other Activities

Tools and Languages

  • GEMS/SIMICS full-system CMP simulator, ATOM instrumentation tool, BOCHS emulator, SESC and CMP$im system simulators
  • PSPICE, Capture CIS, MATLAB, Intel VTune analyzer, ThreadTracker, ThreadProfiler, Pipetrace Viewer, TuningFork
  • BIOS, Extensible Firmware Interface (EFO) -- TIANO
  • Verilog, C, C++, Java, Assembly, Unix, Perl

Courses