Carole-Jean Wu

Engineering Quad.
Olden Street
Princeton University
Princeton, NJ 08540

Email: carolewu [at] princeton edu
Phone: (607) 592-6397

I am fourth-year Ph.D. student in the Department of Electrical Engineering at Princeton University. My advisor is Margaret Martonosi, and I am a member of the Parapet Research Group.

My research interests focus on shared resource management for CMP systems. In particular, I investigate hardware techniques in various granularity levels that assist the management of the last-level shared CMP caches, targeting at performance throughput and quality of service. I am also interested in techniques that exploit potential parallelism hidden in multi-threaded applications on CMP systems. I have looked into both transactional memory works, as well as data-centric synchronization approaches, that grant granularity levels other than simply coarse- or fine-grained parallelism.

Currently I lead the Computer Architecture Reading Group (CARG) in the Departments of Electrical Engineering and Computer Science at Princeton University. Computer Architecture Day(s) at Princeton 2009 organized by us has been a splendid success.

I graduated from School of Electrical and Computer Engineering at Cornell University in 2006, where I worked with Jose Martinez.
 
My resume can be found here.

Education

  • Princeton University, School of Engineering and Applied Science, Princeton, NJ [9/2006 – present]
      3rd-year Ph.D. Candidate in Electrical Engineering
      M.A. in Electrical Engineering (received in 5/2008)

  • Cornell University, College of Engineering, Ithaca, NY [9/2002 – 5/2006]
      B.S. in Electrical and Computer Engineering
      Dean’s List: 2003 2004 2005
      Cum Laude Honors

Publication

Research Talks

Other Talks

  • Building Self Confidence.
      [presented with Prof. Mary Irwin Jane (Penn State University) in Computing Research Association for Women (CRA-W) GradCohort '09]
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Work Experience

  • Engineering Intern @ Platform Software Development, Google Inc. [6/2009 – 8/2009]

      Developed a portfolio of application-level power prediction algorithms for Google data centers. This portfolio includes machine learning algorithms and linear regression techniques that exploit application CPU/power utilization history as well as algorithms that simply react to demand.
      Analyzed Google benchmark and random CPU utilization traces sampled in production environment. Evaluated the effectiveness in prediction accuracy and the usability of the studied algorithms for representative workloads.

  • Graduate Technical Intern @ CTG-STL-PSL, Intel Corporation [6/2008 – 8/2008]

      Analyzed performance and scalability issues related to System Management mode (SMM) on Intel's many-core and Tera-scale platforms.

  • Research Intern @ IBM TJ Waston Research Lab [6/2007 – 8/2007]


  • Technical Intern @ SSG-AET-ATP, Intel Corporation [5/2005 – 8/2005]

      Profiled and characterized threading behaviors of various applications using Intel ThreadTracker, Thread Profiler and VTune performance analyzer.
      Generated multi-threaded traces for IA32 pre-Si simulations for various applications, validated traces were representative, and performed pre-Si architectural analysis.

  • Technical Intern @ SSG-AET-ATP, Intel Corporation [8/2004 – 12/2004]

      Built RT viewer, a graphical tool, that characterizes threading behavior of an application in the pre-Si environment in a multi-core/multi-processor system (using C++).
      Debugged a media decoder for Microsoft and analyzed performance using Intel VTune performance analyzer.

Other Activities

Tools

  • I use GEMS, a full system simulator, on top of SIMICS, a functional processor model, , as a toolset to evaluate my architectural proposals.

Courses