Computer Architecture 101-- Cache and Multi-Level Caches: How to Design Them?

Are you interested in Computer Architecture but do not know much about it? Do you know how Intel Core2 Duo enables your MacBook Pro to surf on Safari while you listen to music on iTunes? Do you know how fast your game applications respond depends not only on how fast your processor (a.k.a CPU) runs but also on how big your memory (a.k.a. RAM) is?

In this seminar, I will show you how today's multi-core CPUs and cache memories work synergistically for you to experience high-performance computing. Also, you will learn the function and the importance of today's multi-level cache hierarchy and the design challenges faced by computer architects. You will walk away with a better understanding of how your computer can juggle with many applications at the same time and also what challenges chip-maker companies like Intel and AMD are currently facing.

Seminar Time: 11-12:30pm Wednesday 11/30/2011
Location: Friend 110

**Light snacks will be provided.

Space is limited. Please RSVP to carolewu@princeton.edu if you plan to attend. 


Speaker Bio:
Carole-Jean Wu is a Ph.D. student in the Electrical Engineering Department of Princeton University. Her research focuses on shared resource management for Chip-Multiprocessor (CMP) systems. In particular, she investigates software and hardware techniques to assist in the management of the last-level shared caches, targeting performance throughput and quality of service. She has looked into transactional memory as well as data-centric synchronization approaches to explore potential thread-level parallelism in modern workloads.

Carole-Jean Wu has interned with Intel, IBM, and Google and is the recipient of the 2011-12 Intel PhD Fellowship Award. Prior to Princeton, Wu earned her B.S. in Electrical and Computer Engineering from Cornell University.