SHiP: Signature-based Hit Predictor for High Performance Caching

         Carole-Jean Wu*, Aamer Jaleel, William Hasenplaugh,
         Margaret Martonosi, Simon Steely Jr., and Joel Emer

The shared last-level caches in CMPs play an important role in improving 
application performance and reducing off-chip memory bandwidth 
requirements. In order to use LLCs more efficiently, recent research has 
shown that changing the re-reference prediction on cache insertions and 
cache hits can significantly improve cache performance. A fundamental 
challenge, however, is how to best predict the re-reference pattern of 
an incoming cacheline.

This paper shows that cache performance can be improved by correlating 
the re-reference behavior of a cacheline with a unique signature. We 
investigate the use of memory region, program counter, and instruction 
sequence history based signatures. We also propose a novel 
Signature-based Hit Predictor (SHiP) to learn the re-reference 
behavior of cachelines belonging to each signature. Overall, we find 
that SHiP offers substantial improvements over the baseline LRU 
replacement and state-of-the-art replacement policy proposals. On 
average, SHiP improves sequential and multiprogrammed application 
performance by roughly 10% and 12% over LRU replacement, respectively. 
Compared to the recent replacement policy proposals such as SLRU 
and SDBP, SHiP nearly doubles the performance gains while requiring 
less hardware overhead.


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* This work is done during Carole-Jean's internship with Intel VSSAD.