At the Nanostructure Laboratory, we demonstrated a silicon single-electron MOS memory that consists of (a) a narrow channel MOSFET with a width (approx. 7 nm) smaller than the Debye screening length of a single electron; and (b) a nanoscale polysilicon dot (approx. 7 nm x 7 nm) as the floating gate embedded between the channel and the control gate. We have observed that storing one electron on the floating gate can screen the channel from the potential on the contron gate, leading to a discrete shift in the threshold voltage, a staircase relationship between the charging voltage and the shift, and a self-limiting charging process.

By clicking on the links below you can take a look at viewgraphs which give further information about the research performed at the laboratory on this kind of memory.

Titlepage
Highlights
Floating Gate MOS Memory
Silicon Single-Electron MOS Memory
Summary of Device Parameters
Scanning Electron Micrograph of a Si SEMM
Measurement Setup
Discrete Shift in Threshold Voltage
Threshold Voltage Shift vs. Charging Voltage
V_th Shift Independent of Charging Time
V_th Shift due to Store of a Single Electron
Self-limited Charging Process