Daniel Lustig

Ph.D. Candidate
Department of Electrical Engineering
Princeton University

Engineering Quadrangle, Olden St.
Princeton, NJ 08544
dlustig (at) princeton (dot) edu

Office: CS 214

I am currently a fourth-year Ph.D. student studying computer architecture in the Electrical Engineering Department at Princeton University. I am a member of MRMGroup, and my advisor is Prof. Margaret Martonosi (CS).

Bio

I grew up in the suburbs of Baltimore, MD. For my undergrad, I went to the University of Pennsylvania (which, as Penn students like to point out, is not the same as Penn State...) in Philadelphia, where I earned my bachelors degree in Electrical Engineering and Mathematics. At Penn, I was a member of mLAB, which is supervised by Prof. Rahul Mangharam.

My CV is available here.

Research

My research is in the field of computer architecture. My current work looks at designing efficient memory systems and synchronization mechanisms for CPU+GPU (or other heterogeneous) systems. Existing synchronization mechanisms (such as kernel boundaries or barriers) are slow and coarse-grained, which costs a significant amount of performance. I am looking at more efficient methods for tracking dependencies and the use of faster, finer-grained synchronization.

Publications

Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Crago, Daniel Lustig, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Vladimir Pavlov, Randy Allmon, Rachid Rayess, Stephen Maresh, and Joel Emer, "Triggered Instructions: A Control Paradigm for Spatially-Programmed Architectures", 40th International Symposium on Computer Architecture (ISCA), Tel Aviv, Israel, June 2013 (to appear).

Daniel Lustig, Abhishek Bhattacharjee, and Margaret Martonosi, "TLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level TLBs", ACM Transactions on Architecture and Code Optimization (TACO), 10 (1), April 2013.

Daniel Lustig and Margaret Martonosi, "Reducing GPU Offload Latency via Fine-Grained CPU-GPU Synchronization", 19th IEEE International Symposium on High Performance Computer Architecture (HPCA), Shenzhen, China, February 2013. [PDF] [Project Page]

Abhishek Bhattacharjee, Daniel Lustig, and Margaret Martonosi, "Shared Last-Level TLBs for Chip Multiprocessors", 17th International Symposium on High Performance Computer Architecture (HPCA), San Antonio, TX, February 2011. [PDF]

Daniel Lustig, "The Algebraic Independence of the Sum of Divisors Functions", Journal of Number Theory, 130 (11), November 2010. [PDF]