- N. K. Jha and D. Chen, Editors, Nanoelectronic Circuit Design, Springer, 2011.
- Z. Kohavi and N. K. Jha, Switching and Finite Automata Theory, 3rd ed., Cambridge University Press, UK, 2009.
- N. K. Jha and S. Gupta, Testing of Digital Systems, Cambridge University Press, UK, 2003.
- A. Raghunathan, N. K. Jha, and S. Dey, High-Level Power Analysis and Optimization, Kluwer Academic Publishers, MA, 1998.
- N. K. Jha and S. Kundu, Testing and Reliable Design of CMOS Circuits, Kluwer Academic Publishers, MA, 1990.
- Y. Kim, W. Lee, A. Raghunathan, V. Raghunathan, and N. K. Jha, ``Reliability and security considerations for implantable and wearable medical devices," book chapter in Implantable Biomedical Microsystems: Design Principles and Applications, Elsevier Science and Technology, 2014.
- D. Bhattacharya and N. K. Jha, ``FinFETs: From devices to architectures," book chapter in Digitally-assisted Analog and Analog-assisted Digital IC Design, Cambridge University Press, 2014.
- C. Li, M. Zhang, A. Raghunathan, and N. K. Jha, ``Attacking and defending a diabetes therapy system," book chapter in Security and Privacy for Implantable Medical Devices, Springer, 2013.
- P. Mishra, A. Muttreja, and N. K. Jha, ``FinFET circuit design," book chapter in Nanoelectronic Circuit Design, Springer, 2011.
- W. Zhang, N. K. Jha, and L. Shang, ``A hybrid nano/CMOS dynamically reconfigurable system," book chapter in Nanoelectronic Circuit Design, Springer, 2011.
- L. Shang, R. P. Dick, and N. K. Jha, ``High-level synthesis algorithms for power and temperature minimization," book chapter in High-level Synthesis: From Algorithm to Digital Circuit, Springer-Verlag, 2008.
- M. Tahoori, N. K. Jha, and I. Bahar, ``Testing aspects of nanotechnology trends," book chapter in System-on-Chip Test Architectures: Nanometer Design for Testability, Elsevier, 2008.
- F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, ``A framework for for extensible processor based MPSoC design," book chapter in Designing Embedded Processors: Low Power Perspective, Springer, 2007.
- N. K. Jha, ``Low power system scheduling, synthesis and displays," book chapter in System-on-chip, IEE, 2006.
- D. Arora, S. Ravi, A. Raghunathan, and N. K. Jha, ``Architectural enhancements for secure embedded processing," book chapter in Security and Embedded Systems, IOS Press, 2006.
- P. Gupta, R. Zhang, and N. K. Jha, ``Logic synthesis for threshold and majority logic," book chapter in Emerging Brain-inspired Nanoarchitectures, World Scientific, 2006.
- R. P. Dick, L. Shang, and N. K. Jha, ``Power-aware architectural synthesis," book chapter in Low Power and Electronics section of the VLSI Handbook, CRC Press, 2006.
- T. K. Tan, A. Raghunathan, and N. K. Jha, ``Software architectural transformations: A new approach to low energy embedded software," book chapter in Embedded Software, Kluwer Academic Publishers, 2003.
- A. Raghunathan, S. Dey and N. K. Jha, ``Glitch analysis and reduction in register transfer level power optimization,'' paper reprinted in a book titled Low Power CMOS Design, edited by A. Chandrakasan and R. Brodersen, IEEE Press, 1997.
- S. Yajnik and N. K. Jha, ``Design and analysis of algorithm-based fault tolerant multiprocessor systems,'' book chapter in Foundations of Dependable Computing: Paradigms for Dependable Applications, Kluwer Academic Publishers, MA, 1994.

- X. Dai and N. K. Jha, ``Improving convergence and simulation time of
quantum hydrodynamic simulation: Application to extraction of best 10nm
FinFET parameter values," accepted for publication in
*IEEE Trans. on VLSI Systems*. - D. Bhattacharya and N. K. Jha, ``Ultra-high density monolithic 3-D
FinFET SRAM with enhanced read stability," accepted for publication in
*IEEE Trans. on Circuits and Systems I*. - X. Chen and N. K. Jha, ``Reducing wire and energy overheads of the
SMART NoC using a setup request network," accepted for publication in
*IEEE Trans. on VLSI Systems*. - A. M. Nia, S. Sur-Kolay, A. Raghunathan, and N. K. Jha,
``Physiological information leakage: A new frontier in health
information security," accepted for publication in
*IEEE Trans. on Emerging Topics in Computing*. - J. Lu, N. Verma, and N. K. Jha, ``Compressed signal processing on
Nyquist-sampled signals," accepted for publication in
*IEEE Trans. on Computers*. - X. Chen and N. K. Jha, ``A 3D CPU-FPGA-DRAM hybrid architecture for
low-power computation,"
*IEEE Trans. on VLSI Systems*, May 2016. - A. Tang, X. Gao, L.-Y. Chen, and N. K. Jha, ``Delay/power modeling
and optimization of FinFET circuit modules under PVT variations: Applications
to the 14nm technology node,"
*ACM Journal of Emerging Technologies in Computing Systems*, May 2016. - S. Chaudhuri and N. K. Jha, ``Ultra-low-leakage and high-performance
logic circuit design using multi-parameter asymmetric FinFETs,"
*ACM Journal of Emerging Technologies in Computing Systems*, May 2016. - A. Tang and N. K. Jha, ``GenFin: Genetic algorithm-based multiobjective
statistical FinFET logic circuit optimization using incremental
statistical analysis,"
*IEEE Trans. on VLSI Systems*, Mar. 2016. - D. Bhattacharya and N. K. Jha, ``TCAD-assisted capacitance
extraction of FinFET SRAM and logic arrays,"
*IEEE Trans. on VLSI Systems*, Jan. 2016. - M. Mozaffari-Kermani, S. Sur-Kolay, A. Raghunathan, and N. K. Jha,
``Systematic poisoning attacks on and defenses for biomedical machine
learning,"
*IEEE Journal of Biomedical and Health Informatics*, Nov. 2015. - T.-J. Lin, W. Zhang, and N. K. Jha, ``FDR 2.0: A low-power
dynamically reconfigurable architecture and its FinFET implementation,"
*IEEE Trans. on VLSI Systems*, Oct. 2015. - X. Chen and N. K. Jha, ``gem5-PVT: A framework for FinFET system
simulation under PVT variations,"
*ACM Journal of Emerging Technologies in Computing Systems*, Sept. 2015. - A. Tang, Y. Yang, C.-Y. Lee, and N. K. Jha, ``McPAT-PVT: Delay and
power modeling framework for FinFET processor architectures
under PVT variations,"
*IEEE Trans. on VLSI Systems*, Sept. 2015. - C.-C. Lin, S. Sur-Kolay, and N. K. Jha, ``PAQCS: Physical
design-aware fault-tolerant quantum circuit synthesis,"
*IEEE Trans. on VLSI Systems*, July 2015. - A. M. Nia, M. Mozaffari-Kermani, S. Sur-Kolay, A. Raghunathan, and
N. K. Jha, ``Energy-efficient long-term continuous personal health
monitoring,"
*IEEE Trans. on Multi-Scale Computing Systems*, June 2015. - D. Bhattacharya, A. N. Bhoj, and N. K. Jha, ``Design of efficient
content addressable memories in high-performance FinFET technology,"
*IEEE Trans. on VLSI Systems*, May 2015. - M. Shoaib, N. K. Jha, and N. Verma, ``Signal processing with
direct computations on compressively-sensed data,"
*IEEE Trans. on VLSI Systems*, Jan. 2015. - T.-J. Lin, W. Zhang, and N. K. Jha, ``FDR: A fine-grain
dynamically reconfigurable architecture aimed at reducing the FPGA-ASIC
gaps,"
*IEEE Trans. on VLSI Systems*, Dec. 2014. - Y. Yang and N. K. Jha, ``FinPrin: FinFET logic circuit analysis
and optimization under PVT variations,"
*IEEE Trans. on VLSI Systems*, Dec. 2014. - S. Chaudhuri and N. K. Jha, ``Accurate leakage/delay estimation
for FinFET standard cells under PVT variations using the response
surface methodology,"
*ACM Journal of Emerging Technologies in Computing Systems*, Nov. 2014. - D. Bhattacharya and N. K. Jha, ``FinFETs: From devices to
architectures,"
*Advances in Electronics*, Hindawi Publishing Corp., Sept. 2014 (invited outlook article). - C.-C. Lin, A. Chakrabarti, and N. K. Jha, ``QLib: Quantum module
library,"
*ACM Journal of Emerging Technologies in Computing Systems*, Sept. 2014. - X. Chen and N. K. Jha, ``Ultra-low-leakage chip multiprocessor
design with hybrid FinFET logic styles,"
*ACM Journal of Emerging Technologies in Computing Systems*, Sept. 2014. - M. Zhang, A. Raghunathan, and N. K. Jha, ``Addressing the
trustworthiness of medical devices and body area networks,"
*Proceedings of IEEE*, Aug. 2014. - C. Lin, A. Chakrabarti, and N. K. Jha, ``FTQLS: Fault-tolerant
quantum logic synthesis,"
*IEEE Trans. on VLSI Systems*, June 2014. - C.-Y. Lee and N. K. Jha, ``FinCANON: A PVT-aware integrated delay and
power modeling framework for FinFET-based caches and on-chip networks,"
*IEEE Trans. on VLSI Systems*, May 2014. - M. Shoaib, K. H. Lee, N. K. Jha, and N. Verma, ``A 0.6-107uW
energy-scalable processor for seizure detection with compressively-sensed
EEG,"
*IEEE Trans. on Circuits and Systems I*, Apr. 2014. - S. Chaudhuri and N. K. Jha, ``3D vs. 2D device simulation of
FinFET logic gates under PVT variations,"
*ACM Journal of Emerging Technologies in Computing Systems*, Apr. 2014. - M. Zhang, A. Raghunathan, and N. K. Jha, ``A defense framework
against malware and vulnerability exploits,"
*Springer International Journal of Information Security*, Mar. 2014. - A. N. Bhoj and N. K. Jha, ``Parasitics-aware design of symmetric
and asymmetric gate-workfunction FinFET SRAMs,"
*IEEE Trans. on VLSI Systems*, Mar. 2014. - C. Lin and N. K. Jha, ``RMDDS: Reed-Muller decision diagram
synthesis of reversible logic circuits,"
*ACM Journal of Emerging Technologies in Computing Systems*, Feb. 2014. - M. Zhang, A. Raghunathan, and N. K. Jha, ``MedMon: Securing
medical devices through wireless monitoring and anomaly detection,"
*IEEE Trans. on Biomedical Circuits and Systems*, Dec. 2013. - J. W. Chuah, A. Raghunathan, and N. K. Jha, ``ROBESim: A
retrofit-oriented building energy simulator based on EnergyPlus,"
*Elsevier Energy and Buildings Journal*, Nov. 2013. - A. N. Bhoj, R. V. Joshi, and N. K. Jha, ``3D-TCAD based parasitic
capacitance extraction for emerging multi-gate devices and circuits,"
*IEEE Trans. on VLSI Systems*, Nov. 2013. - C. Lin, A. Chakrabarti, and N. K. Jha, ``Optimized quantum gate
library for various physical machine descriptions,"
*IEEE Trans. on VLSI Systems*, Nov. 2013. - A. N. Bhoj and N. K. Jha, ``Design of logic gates and flip-flops
in high-performance FinFET technology,"
*IEEE Trans. on VLSI Systems*, Nov. 2013. - M. Shoaib, N. K. Jha, and N. Verma, ``Algorithm-driven
architectural design space exploration of domain-specific medical-sensor
processors,"
*IEEE Trans. on VLSI Systems*, Oct. 2013. - C.-Y. Lee and N. K. Jha, ``Variable-pipeline-stage router,"
*IEEE Trans. on VLSI Systems*, Sept. 2013. - C. Li, A. Raghunathan, and N. K. Jha, ``Improving the
trustworthiness of medical device software with formal verification
methods,"
*IEEE Embedded System Letters*, Sept. 2013. - A. Tang and N. K. Jha, ``Design space exploration of FinFET cache,"
*ACM Journal of Emerging Technologies in Computing Systems*, Sept. 2013. - A. Tang and N. K. Jha, ``Thermal characterization of test
techniques for FinFET and 3D integrated circuits,"
*ACM Journal of Emerging Technologies in Computing Systems*, Feb. 2013. - A. N. Bhoj, R. V. Joshi, and N. K. Jha, ``Efficient methodologies for
3D-TCAD modeling of emerging devices and circuits,"
*IEEE Trans. on Computer-Aided Design*, Jan. 2013. - T.-J. Lin, W. Zhang, and N. K. Jha, ``SRAM-based NATURE: A
dynamically reconfigurable FPGA based on 10T low-power SRAM,"
*IEEE Trans. on VLSI Systems*, Nov. 2012. - C. Li, A. Raghunathan, and N. K. Jha, ``A trusted virtual machine
in an untrusted management environment,"
*IEEE Trans. on Services Computing*, Oct.-Dec. 2012. - D. Arora, N. Aaraj, A. Raghunathan, and N. K. Jha, ``INVISIOS: A
lightweight, minimally intrusive secure execution environment,"
*ACM Trans. on Embedded Computing Systems*, Sept. 2012. - C. Li, A. Raghunathan, and N. K. Jha, ``Secure reconfiguration of
software defined radio,"
*ACM Trans. on Embedded Computing Systems*, Mar. 2012. - A. N. Bhoj, M. Simsir, and N. K. Jha, ``Fault models for logic
circuits in the multigate era,"
*IEEE Trans. on Nanotechnology*, Jan. 2012. - M. Zhang and N. K. Jha, ``FinFET-based power management for DPA
resistance with low overhead,"
*ACM Journal of Emerging Technologies in Computing Systems*, Aug. 2011. - N. Aaraj, A. Raghunathan, and N. K. Jha, ``A framework for
defending embedded systems against software attacks,"
*ACM Trans. on Embedded Computing Systems*, Apr. 2011. - A. N. Bhoj and N. K. Jha, ``Gated-diode FinFET DRAMs: Device and
circuit design considerations,"
*ACM Journal of Emerging Technologies in Computing Systems*, Dec. 2010. - W. Zhang, N. K. Jha, and L. Shang, ``Low-power 3D nano/CMOS hybrid
dynamically reconfigurable architecture,"
*ACM Journal of Emerging Technologies in Computing Systems*, Aug. 2010. - C.-Y. Lee and N. K. Jha, ``FinFET-based power simulator for
interconnection networks,"
*ACM Journal of Emerging Technologies in Computing Systems*, Mar. 2010. - W. Zhang, N. K. Jha, and L. Shang, ``Design space exploration
and data memory architecture design for a hybrid nano/CMOS
dynamically reconfigurable architecture,"
*ACM Journal of Emerging Technologies in Computing Systems*, Nov. 2009. - W. Zhang, N. K. Jha, and L. Shang, ``A hybrid CMOS/nanotube
dynamically reconfigurable system -- Part I: Architecture,"
*ACM Journal of Emerging Technologies in Computing Systems*, Nov. 2009. - W. Zhang, L. Shang, and N. K. Jha, ``A hybrid CMOS/nanotube
dynamically reconfigurable system -- Part II: Design optimization flow,"
*ACM Journal of Emerging Technologies in Computing Systems*, Aug. 2009. - M. O. Simsir, S. Cadambi, F. Ivancic, M. Roetteler, and N. K. Jha,
``A hybrid nano-CMOS architecture for defect and fault tolerance,"
*ACM Journal of Emerging Technologies in Computing Systems*, Aug. 2009. - P. Mishra, A. Muttreja, and N. K. Jha, ``Low-power FinFET circuit
synthesis using multiple supply and threshold voltages,"
*ACM Journal of Emerging Technologies in Computing Systems*, July 2009. - L. Lingappan, V. Gangaram, N. K. Jha, and S. Chakravarty, ``Fast
enhancement of validation test sets for improving the stuck-at fault
coverage of RTL circuits,"
*IEEE Trans. on VLSI Systems*, May 2009. - N. Aaraj, A. Raghunathan, S. Ravi, and N. K. Jha, ``Analysis and
design of a software-based trusted platform module for
embedded systems,"
*ACM Trans. on Embedded Computing Systems*, Dec. 2008. - P. Gupta, R. Zhang, and N. K. Jha, ``Automatic test pattern
generation for combinational threshold logic networks,"
*IEEE Trans. on VLSI Systems*, Aug. 2008. - Y. Fei, L. Zhong, and N. K. Jha, "An energy-aware framework for dynamic
software management in mobile computing systems,"
*ACM Trans. on Embedded Computing Systems*, Apr. 2008. - J. Donald and N. K. Jha, ``Reversible logic synthesis with Fredkin
and Peres gates,"
*ACM Journal of Emerging Technologies in Computing Systems*, Mar. 2008. - A. Kumar, L.-S. Peh, P. Kundu, and N. K. Jha, ``Towards ideal
on-chip communication using express virtual channels,"
*IEEE Micro Magazine*, Jan./Feb. 2008 (Top Picks of 2007 Computer Architecture Conferences). - Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, `` Energy-optimizing
source code transformations for operating system driven embedded software,"
*ACM Trans. on Embedded Computing Systems*, Dec. 2007. - A. Kumar, L. Shang, L.-S. Peh, and N. K. Jha, ``System-level dynamic
thermal management for high performance microprocessors,"
*IEEE Trans. on Computer-Aided Design*, Dec. 2007. - C. Huang, S. Ravi, A. Raghunathan, and N. K. Jha, ``Generation of
heterogeneous distributed architectures for memory-intensive applications
through high-level synthesis,"
*IEEE Trans. on VLSI Systems*, Nov. 2007. - F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, ``A synthesis
methodology for hybrid custom instruction and co-processor generation for
extensible processors,"
*IEEE Trans. on Computer-Aided Design*, Nov. 2007. - A. Muttreja, A. Raghunathan, S. Ravi, and N. K. Jha, ``Hybrid
simulation for energy estimation of embedded software,"
*IEEE Trans. on Computer-Aided Design*, Oct. 2007. - R. Zhang, P. Gupta, and N. K. Jha, ``Majority and minority network
synthesis with application to QCA, SET and TPL based nanotechnologies,"
*IEEE Trans. on Computer-Aided Design*, July 2007. - L. Lingappan and N. K. Jha, ``Efficient design for testability
solution based on unsatisfiability for register-transfer level
circuits,"
*IEEE Trans. on Computer-Aided Design*, July 2007. - J. Luo and N. K. Jha, ``Power-efficient scheduling for heterogeneous
distributed real-time embedded systems,''
*IEEE Trans. on Computer-Aided Design*, June 2007. - D. Arora, A. Raghunathan, S. Ravi, and N. K. Jha, ``Exploring
software partitions for fast security processing on a multiprocessor
mobile SoC,"
*IEEE Trans. on VLSI Systems*, June 2007. - D. Arora, A. Raghunathan, S. Ravi, and N. K. Jha, ``Architectural
support for run-time validation of program data properties,"
*IEEE Trans. on VLSI Systems*, May 2007. - N. R. Potlapally, S. Ravi, A. Raghunathan, R. B. Lee and N. K.
Jha, ``Configuration and extension of embedded processors to optimize
IPSec protocol execution,"
*IEEE Trans. on VLSI Systems*, May 2007. - L. Lingappan and N. K. Jha, ``Satisfiability based automatic
test program generation and design for testability for microprocessors,"
*IEEE Trans. on VLSI Systems*, May 2007. - N. Potlapally, A. Raghunathan, S. Ravi, N. K. Jha, and R. B. Lee,
``Aiding side-channel attacks on cryptographic software with satisfiability-based
analysis,"
*IEEE Trans. on VLSI Systems*, Apr. 2007. - J. Luo, N. K. Jha, and L.-S. Peh, ``Simultaneous dynamic voltage
scaling of processors and communication links in real-time distributed
embedded systems,"
*IEEE Trans. on VLSI Systems*, Apr. 2007. - N. Aaraj, S. Ravi, A. Raghunathan, and N. K. Jha, ``Hybrid
architectures for efficient and accurate face authentication in
embedded systems,"
*IEEE Trans. on VLSI Systems*, Mar. 2007. - L. Shang, R. Dick, and N. K. Jha, ``SLOPES: Hardware-software
co-synthesis of low power real-time distributed embedded systems with
dynamically reconfigurable FPGAs,"
*IEEE Trans. on Computer-Aided Design*, Mar. 2007. - A. Muttreja, A. Raghunathan, S. Ravi, and N. K. Jha, ``Automated
energy/performance macromodeling of embedded software,"
*IEEE Trans. on Computer-Aided Design*, Mar. 2007. - P. Gupta, N. K. Jha, and L. Lingappan, ``A test generation
framework for quantum cellular automata circuits,"
*IEEE Trans. on VLSI Systems*, Jan. 2007. - D. Arora, S. Ravi, A. Raghunathan, and N. K. Jha,
``Hardware-assisted run-time monitoring for secure program execution
on embedded processors,"
*IEEE Trans. on VLSI Systems*, Dec. 2006. - F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, ``A scalable
synthesis methodology for application-specific processors,"
*IEEE Trans. on VLSI Systems*, Nov. 2006. - P. Gupta, A. Agrawal, and N. K. Jha, ``An algorithm for synthesis of
reversible logic circuits,"
*IEEE Trans. on Computer-Aided Design*, Nov. 2006. - L. Zhong and N. K. Jha, ``Dynamic power optimization targeting user
delays in interactive systems,"
*IEEE Trans. on Mobile Computing*, Nov. 2006. - L. Lingappan and N. K. Jha, ``Test volume reduction in
systems-on-chip using heterogeneous and multi-level compression
techniques,"
*IEEE Trans. on Computer-Aided Design*, Oct. 2006. - C. Huang, S. Ravi, A. Raghunathan, and N. K. Jha, ``Use of
computation-unit integrated memories in high-level synthesis,"
*IEEE Trans. on Computer-Aided Design*, Oct. 2006. - L. Zhong, S. Ravi, A. Raghunathan, and N. K. Jha, ``RTL-aware
cycle-accurate functional power estimation,"
*IEEE Trans. on Computer-Aided Design*, Oct. 2006. - F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, ``Application-specific
heterogeneous multiprocessor synthesis using extensible processors,"
*IEEE Trans. on Computer-Aided Design*, Sept. 2006. - K. Vallerio, L. Zhong, and N. K. Jha, ``Energy-efficient graphical
user interface design,"
*IEEE Trans. on Mobile Computing*, July 2006. - L. Lingappan, S. Ravi, and N. K. Jha, ``Satisfiability based
test generation for non-separable RTL controller-datapath circuits,"
*IEEE Trans. on Computer-Aided Design*, vol. 25, Mar. 2006. - N. R. Potlapally, S. Ravi, A. Raghunathan, and N. K. Jha, ``A
study of the energy consumption characteristics of cryptographic
algorithms and security protocols,"
*IEEE Trans. on Mobile Computing*, Feb. 2006. - L. Shang, L.-S. Peh, A. Kumar, and N. K. Jha, ``Temperature-aware
on-chip networks,"
*IEEE Micro*, Jan.-Feb. 2006 (Micro's Top Picks from 2005 Computer Architecture Conferences). - L. Shang, L.-S. Peh, and N. K. Jha, ``PowerHerd: A distributed scheme
for dynamically satisfying peak power constraints in interconnection
networks,"
*IEEE Trans. on Computer-Aided Design*, vol. 25, Jan. 2006. - W. Wang, A. Raghunathan, G. Lakshminarayana, and N. K. Jha, ``Input
space adaptive optimization for embedded software synthesis,"
*IEEE Trans. on Computer-Aided Design*, vol. 24, Nov. 2005. - C. Huang, S. Ravi, A. Raghunathan, and N. K. Jha, ``Generation of
distributed logic-memory architectures through high-level synthesis,''
*IEEE Trans. on Computer-Aided Design,*, vol. 24, Nov. 2005. - L. Yan, J. Luo, and N. K. Jha, ``Joint dynamic voltage scaling and
adaptive body biasing for heterogeneous distributed real-time embedded
systems,"
*IEEE Trans. on Computer-Aided Design*, vol. 24, July 2005. - K. S. Khouri, G. Lakshminarayana, and N. K. Jha, ``Memory binding
for performance optimization of control-flow intensive behavioral
descriptions,"
*IEEE Trans. on VLSI Systems*, vol. 13, May 2005. - N. K. Jha, ``Low power system scheduling, synthesis and displays,"
accepted for publication in
*IEE Proceedings Computer and Digital Techniques*, Special Issue on Embedded Microelectronic Systems: Status and Trends, Mar. 2005 (invited paper). - P. Gupta and N. K. Jha, ``An algorithm for nano-pipelining
of RTD-based circuits and architectures,"
*IEEE Trans. on Nanotechnology*, vol. 4, Mar. 2005. - L. Zhong and N. K. Jha, ``Interconnect-aware high-level synthesis,"
*IEEE Trans. on Computer-Aided Design*, vol. 24, Mar. 2005. - T. K. Tan, A. Raghunathan, and N. K. Jha, ``Energy macro-modeling
of embedded operating systems,''
*ACM Trans. on Embedded Computing Systems*, vol. 4, Feb. 2005. - R. Zhang, P. Gupta, L. Zhong, and N. K. Jha, ``Threshold network
synthesis and optimization and its application to nanotechnologies,"
*IEEE Trans. on Computer-Aided Design*, vol. 24, Jan. 2005. - J. Luo, L. Zhong, Y. Fei, and N. K. Jha, ``Register binding based RTL
power management for control-flow intensive designs,''
*IEEE Trans. on Computer-Aided Design*, vol. 23, Aug. 2004. - W. Wang, A. Raghunathan, N. K. Jha, and S. Dey, ``Resource budgeting
for multi-process high-level synthesis,''
*IEEE Trans. on Computer-Aided Design*, vol. 23, July 2004. - Y. Fei and N. K. Jha, ``Integrated functional partitioning and synthesis
for low power distributed systems of systems-on-a-chip,"
, no. 1, June 2004 (invited paper). - W. Wang, A. Raghunathan, G. Lakshminarayana, and N. K. Jha, ``Input
space adaptive design: A high-level methodology for optimizing energy and
performance,''
*IEEE Trans. on VLSI Systems*, vol. 12, June 2004. - Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, ``A hybrid energy
estimation technique for extensible processors,"
*IEEE Trans. on Computer-Aided Design*, vol. 23, May 2004. - F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, ``Custom instruction
synthesis for extensible processor platforms,"
*IEEE Trans. on Computer-Aided Design*, vol. 23, Feb. 2004. - L. Shang, R. P. Dick, and N. K. Jha, ``DESP: A distributed
economics-based subcontracting protocol for computation distribution in
power-aware mobile ad-hoc networks,''
*IEEE Trans. on Mobile Computing*, Jan.-Mar. 2004.. - G. Lakshminarayana, A. Raghunathan, K. S. Khouri, N. K. Jha, and S. Dey,
``Common-case computation: A high-level energy and performance optimization
technique,''
*IEEE Trans. on Computer-Aided Design*, vol. 23, Jan. 2004. - R. P. Dick and N. K. Jha, ``COWLS: Hardware-software co-synthesis of
wireless low-power distributed embedded client-server systems,''
*IEEE Trans. Computer-Aided Design*, vol. 23, Jan. 2004. - T. K. Tan, A. Raghunathan, and N. K. Jha, ``A simulation framework
for energy consumption analysis of OS-driven embedded applications,''
*IEEE Trans. on Computer-Aided Design*, vol. 22, Sept. 2003. - A. Raghunathan, S. Dey, and N. K. Jha, ``High-level macro-modeling
and estimation techniques for switching activity and power consumption,''
*IEEE Trans. on VLSI Systems*, vol. 11, Aug. 2003. - R. P. Dick, G. Lakshminarayana, A. Raghunathan, and N. K. Jha,
``Analysis of power dissipation in embedded operating systems,''
*IEEE Trans. on Computer-Aided Design*, vol. 22, May 2003. - K. S. Khouri and N. K. Jha, ``Leakage power analysis and reduction
during behavioral synthesis,''
*IEEE Trans. on VLSI Systems*, vol. 10, Dec. 2002. - S. Ravi and N. K. Jha, ``Test synthesis of systems-on-a-chip,''
*IEEE Trans. on Computer-Aided Design*, vol. 21, Oct. 2002. - T. K. Tan, A. Raghunathan, G. Lakshminarayana, and N. K. Jha, ``High-level
energy macro-modeling for embedded software,''
*IEEE Trans. on Computer-Aided Design*, vol. 21, Sept. 2002. - S. Ravi, G. Lakshminarayana, and N. K. Jha, ``High-level test compaction
techniques,''
*IEEE Trans. on Computer-Aided Design*, vol. 21, July 2002. - L. Shang, L.-S. Peh, and N. K. Jha, ``Power-efficient interconnection networks:
Dynamic voltage scaling with links,''
*IEEE Computer Architecture Letters*, vol. 1, no. 2, July 2002. - S. Ravi, G. Lakshminarayana, and N. K. Jha, ``TAO: Regular expression
based register-transfer level testability analysis and optimization,''
*IEEE Trans. on VLSI Systems*, vol. 9, Dec. 2001. - S. Ravi, I. Ghosh, V. Boppana, and N. K. Jha, ``A fault diagnosis based
technique for establishing RTL and gate-level correspondences,''
*IEEE Trans. on Computer-Aided Design*, vol. 20, Dec. 2001. - S. Ravi, G. Lakshminarayana, and N. K. Jha, ``Testing of core-based
systems-on-a-chip,''
*IEEE Trans. on Computer-Aided Design*, vol. 20, Mar. 2001. - K. S. Khouri and N. K. Jha, ``Clock selection for performance
optimization of control-flow intensive behaviors,''
*IEEE Trans. on Computer-Aided Design*, vol. 20, Jan. 2001. - G. Lakshminarayana, A. Raghunathan, and N. K. Jha, ``Behavioral synthesis
of fault secure controller/datapaths based on aliasing probability analysis,''
*IEEE Trans. on Computers*, vol. 49, Sept. 2000. - S. Ravi, G. Lakshminarayana, and N. K. Jha, ``TAO-BIST: A framework
for testability analysis and optimization for built-in self-test of RTL
circuits,''
*IEEE Trans. on Computer-Aided Design*, vol. 19, Aug. 2000. - I. Ghosh, S. Dey, and N. K. Jha, ``A fast and low cost testing
technique for core-based system chips,''
*IEEE Trans. on Computer-Aided Design*, vol. 19, Aug. 2000. - G. Lakshminarayana, A. Raghunathan, and N. K. Jha, ``Incorporating
speculative execution into scheduling of control-flow intensive designs,''
*IEEE Trans. on Computer-Aided Design*, vol. 19, Mar. 2000. - I. Ghosh, N. K. Jha, and S. Bhawmik, ``A BIST scheme for RTL
circuits based on symbolic testability analysis,''
*IEEE Trans. on Computer-Aided Design*, vol. 19, Jan. 2000. - K. S. Khouri, G. Lakshminarayana, and N. K. Jha, ``High-level synthesis
of low power control-flow intensive circuits,''
*IEEE Trans. on Computer-Aided Design*, vol. 18, Dec. 1999. - I. Ghosh, N. K. Jha, and S. Dey, ``A low overhead design for testability
and test generation technique for core-based systems-on-a-chip,''
*IEEE Trans. on Computer-Aided Design*, vol. 18, Nov. 1999. - G. Lakshminarayana and N. K. Jha, ``FACT: A framework for applying
throughput and power optimizing transformations to control-flow intensive
behavioral descriptions,''
*IEEE Trans. on Computer-Aided Design*, vol. 18, Nov. 1999. - S. Dey, A. Raghunathan, N. K. Jha, and K. Wakabayashi, ``Controller-based
power management for control-flow intensive designs,''
*IEEE Trans. on Computer-Aided Design*, vol. 18, Oct. 1999. - A. Raghunathan, S. Dey, and N. K. Jha, ``Register transfer level power
optimization with emphasis on glitch analysis and reduction,''
*IEEE Trans. on Computer-Aided Design*, vol. 18, Aug. 1999. - G. Lakshminarayana, K. S. Khouri, and N. K. Jha, ``Wavesched: A novel
scheduling technique for control-flow intensive designs,''
*IEEE Trans. on Computer-Aided Design*, vol. 18, May 1999. - B. Dave and N. K. Jha, ``COFTA: Hardware-software co-synthesis of
heterogeneous distributed embedded systems for low overhead fault tolerance,''
*IEEE Trans. on Computers*, vol. 48, Apr. 1999. - I. Ghosh, A. Raghunathan, and N. K. Jha, ``Hierarchical test generation
and design for testability methods for ASPPs and ASIPs,''
*IEEE Trans. on Computer-Aided Design*, vol. 18, Mar. 1999. - S. Srinivasan and N. K. Jha, ``Task allocation for safety and reliability
in Distributed Systems,''
*IEEE Trans. on Parallel and Distributed Systems*, vol. 10, Mar. 1999. - G. Lakshminarayana and N. K. Jha, ``High-level synthesis of
power-optimized and area-optimized circuits from hierarchical data-flow
intensive behaviors,''
*IEEE Trans. on Computer-Aided Design*, vol. 18, Mar. 1999. - B. Dave, G. Lakshminarayana and N. K. Jha, ``COSYN: Hardware-software
co-synthesis of embedded systems,''
*IEEE Trans. on VLSI Systems*, vol. 7, Mar. 1999. - G. Lakshminarayana, A. Raghunathan, N. K. Jha and S. Dey, ``Power
management in high-level synthesis,''
*IEEE Trans. on VLSI Systems*, vol. 7, Mar. 1999. - S. Bhatia and N. K. Jha, ``Integration of hierarchical test generation
with behavioral synthesis of controller and data path circuits,''
*IEEE Trans. on VLSI Systems*, vol. 6, Dec. 1998. - I. Ghosh and N. K. Jha, ``High-level test synthesis: A survey,''
*Integration, The VLSI Journal*, vol. 26, Dec. 1998. - B. Dave and N. K. Jha, ``COHRA: Hardware-software co-synthesis of
hierarchical heterogeneous distributed embedded systems,''
*IEEE Trans. on Computer-Aided Design*, vol. 17, Oct. 1998. - R. P. Dick and N. K. Jha,
``MOGAC: A multiobjective genetic algorithm
for the hardware-software co-synthesis of distributed embedded systems,''
*IEEE Trans. on Computer-Aided Design*, vol. 17, Oct. 1998. - I. Ghosh, A. Raghunathan and N. K. Jha, ``A design for testability
technique for register-transfer level circuits using control/data flow
extraction,''
*IEEE Trans. on Computer-Aided Design*, vol. 17, Aug. 1998. - S. M. Nowick, N. K. Jha and F.-C. Cheng, ``Synthesis of asynchronous
circuits for stuck-at and robust path delay fault testability,''
*IEEE Trans. on Computer-Aided Design*, vol. 16, Dec. 1997. - A. Raghunathan and N. K. Jha, ``An iterative improvement algorithm for
low power data path synthesis,''
*IEEE Trans. on Computer-Aided Design*, vol. 16, Nov. 1997. - I. Ghosh, A. Raghunathan and N. K. Jha, ``Design for hierarchical
testability of RTL circuits obtained by behavioral synthesis,''
*IEEE Trans. on Computer-Aided Design*, vol. 16, pp. 1001-1014, Sept. 1997. - S. Yajnik and N. K. Jha, ``Analysis and randomized design of
algorithm-based fault tolerant multiprocessor systems under an extended
model,''
*IEEE Trans. on Parallel & Distributed Systems*, vol. 8, pp. 757-768, July 1997. - S. Yajnik and N. K. Jha, ``Graceful degradation in algorithm-based fault
tolerant multiprocessor systems,''
*IEEE Trans. on Parallel & Distributed Systems*, vol. 8, pp. 137-153, Feb. 1997. - S. Bhatia and N. K. Jha, ``Synthesis for parallel scan: Applications to
partial scan and robust path delay fault testability,''
*IEEE Trans. on Computer-Aided Design*, vol. 15, pp. 228-243, Feb. 1996. - B. Vinnakota and N. K. Jha, ``Design of algorithm-based fault-tolerant
multiprocessor systems for concurrent error detection and fault diagnosis,''
*IEEE Trans. on Parallel & Distributed Systems*, vol. 5, pp. 1099-1106, Oct. 1994. - S.-J. Wang and N. K. Jha, ``Algorithm-based fault tolerance for FFT
networks,''
*IEEE Trans. on Computers*, vol. 43, pp. 849-854, July 1994. - J. Rexford and N. K. Jha, ``Partitioned encoding schemes for
algorithm-based fault tolerance in massively parallel systems,''
*IEEE Trans. on Parallel & Distributed Systems*, vol. 5, pp. 649-653, June 1994. - S. Burns and N. K. Jha, ``A totally self-checking checker for a parallel
unordered coding scheme,''
*IEEE Trans. on Computers*, vol. 43, Apr. 1994. - B. Vinnakota and N. K. Jha, ``Synthesis of algorithm-based fault tolerant
systems from dependence graphs,''
*IEEE Trans. on Parallel and Distributed Systems*, vol. 4, pp. 864-874, Aug. 1993. - B. Vinnakota and N. K. Jha, ``Diagnosability and diagnosis of
algorithm-based fault tolerant systems,''
*IEEE Trans. on Computers*, vol. 42, pp. 924-937, Aug. 1993. - R. K. Sitaraman and N. K. Jha, ``Optimal design of checks for error
detection and location in fault tolerant multiprocessor systems,''
*IEEE Trans. on Computers*, vol. 42, pp. 780-793, July 1993. - N. K. Jha and S.-J. Wang, ``Design and synthesis of self-checking
VLSI circuits,''
*IEEE Trans. on Computer-Aided Design*, vol. 12, pp. 878-887, June 1993. - N. K. Jha, ``Self-checking DCVS circuits,''
*Hardware and Software Fault Tolerance in Parallel Computing Systems*, Ellis Horwood Ltd., 1993. - N. K. Jha, ``Fault detection in CVS parity trees with application to
strongly self-checking parity and two-rail checkers,''
*IEEE Trans. on Computers*, vol. 42, pp. 179-189, Feb. 1993. - N. K. Jha and A. Ahuja, ``Easily testable non-restoring and restoring
gate-level cellular array dividers,''
*IEEE Trans. on Computer-Aided Design*, vol. 12, pp. 114-123, Jan. 1993. - N. K. Jha and Q. Tong, ``Robustly testable static CMOS parity trees
derived from binary decision diagrams,''
*IEEE J. of Solid-State Circuits*, vol. 26, pp. 1728-1733, Nov. 1991. - S. Kundu, S. M. Reddy, and N. K. Jha, ``Design of robustly testable
combinational logic circuits,''
*IEEE Trans. on Computer-Aided Design*, vol. 10, pp. 1036-1048, Aug. 1991. - A. R. Takach and N. K. Jha, ``Easily testable gate-level and DCVS
multipliers,''
*IEEE Trans. on Computer-Aided Design*, vol. 10, pp. 932-942, July 1991. - K. I. Diamantaras and N. K. Jha, ``A new transition count method for
testing of logic circuits,''
*IEEE Trans. on Computer-Aided Design*, vol. 10, pp. 407-410, Mar. 1991. - Q. Tong and N. K. Jha, ``Design of C-testable DCVS binary array
dividers,''
*IEEE J. of Solid-State Circuits*, vol. 26, no. 2, pp. 134-141, Feb. 1991. - N. K. Jha, ``Totally self-checking checker designs for Bose-Lin, Bose and
Blaum codes,''
*IEEE Trans. on Computer-Aided Design*, vol. 10, pp. 136-143, Jan. 1991. - N. K. Jha and Q. Tong, ``Detection of multiple input bridging and
stuck-on faults in CMOS logic circuits using current monitoring,''
*Int. J. of Computers & Electrical Engineering*, vol. 16, no. 3, pp. 115-124, 1990. - Q. Tong and N. K. Jha, ``Testing of Zipper CMOS logic circuits,''
*IEEE J. of Solid-State Circuits*, vol. 25, no. 3, pp. 877-880, June 1990. - N. K. Jha and Q. Tong, ``Testing of multiple-output domino logic (MODL)
CMOS circuits,''
*IEEE J. of Solid-State Circuits*, vol. 25, no. 3, pp. 800-805, June 1990. - N. K. Jha, ``Strongly fault-secure and strongly self-checking domino-CMOS
implementations of totally self-checking circuits,''
*IEEE Trans. on Computer-Aided Design*, vol. 9, no. 3, pp. 332-336, Mar. 1990. - S.-J. Wang and N. K. Jha, ``Systematic t-error correcting/all
unidirectional error detecting codes with easy encoding/decoding,''
*Int. J. of Computers & Mathematics with Applications*, vol. 20, no. 1, pp. 5-13, 1990. - N. K. Jha, ``Testing of differential cascode voltage switch one-count
generators,''
*IEEE J. of Solid-State Circuits*, vol. 25, no. 1, pp. 246-253, Feb. 1990. - N. K. Jha, ``A new class of symmetric error correcting/unidirectional
error detecting codes,''
*Int. J. of Computers and Mathematics with Applications*, vol. 19, no. 5, pp. 95-104, 1990. - N. K. Jha, ``Comments on `A MOS implementation of totally self-checking
checker for the 1-out-of-3 code',''
*IEEE J. of Solid-State Circuits*, vol. 24, no. 5, pp. 1470-1471, Oct. 1989. - N. K. Jha, ``Robust Testing of CMOS logic circuits,''
*Int. J. of Computers & Electrical Engineering*, vol. 15, no. 1, pp. 19-28, 1989. - N. K. Jha, ``A totally self-checking checker for Borden's code,''
*IEEE Trans. on Computer-Aided Design*, vol. 8, pp. 731-736, July 1989. -
N. K. Jha, ``Separable codes for detecting unidirectional errors,''
*IEEE Trans. on Computer-Aided Design*, vol. 8, pp. 571-574, May 1989. - N. K. Jha and M. B. Vora, ``A t-unidirectional error detecting systematic
code,''
*Int. J. of Computers & Mathematics with Applications*, vol. 16, no. 9, pp. 705-714, 1988. - G. Gupta and N. K. Jha, ``A universal test set for CMOS circuits,''
*IEEE Trans. on Computer-Aided Design*, vol. 7, pp. 590-597, May 1988. - N. K. Jha, ``Multiple stuck-open fault detection in CMOS logic circuits,''
*IEEE Trans. on Computers*, vol. 37, pp. 426-432, Apr. 1988. - N. K. Jha, ``Testing for multiple faults in domino-CMOS logic circuits,''
*IEEE Trans. on Computer-Aided Design*, vol. 7, pp. 109-116, Jan. 1988. - N. K. Jha and J. A. Abraham, ``Techniques for efficiently implementing
totally self-checking checkers in MOS technology,''
*Int. J. of Computers & Mathematics with Applications*, vol. 13, no. 5/6, pp. 555-566, 1987. - N. K. Jha and J. A. Abraham, ``Design of testable CMOS circuits under
arbitrary delays,''
*IEEE Trans. on Computer-Aided Design*, vol. CAD-4, pp. 264-269, July 1985.

- Y. Kim, W. S. Lee, V. Raghunathan, N. K. Jha, and A. Raghunathan,
``Secure wireless implantable and wearable medical devices,"
*Int. Conf. IEEE Engineering in Medicine and Biology Society*, Aug. 2016. - S. Chaudhuri, A. N. Bhoj, D. Bhattacharya, and N. K. Jha, ``Fast FinFET
device simulation under process-voltage variations using an assisted
speed-up mechanism,"
*IEEE Int. Conf. on VLSI Design*, Jan. 2016. - P. Niemann, S. Basu, A. Chakrabarti, N. K. Jha and R. Wille,
``Synthesis of quantum circuits for dedicated physical machine
descriptions,"
*Conference on Reversible Computation*, July 2015. - Y. Kim, W. Lee, A. Raghunathan, V. Raghunathan, and N. K. Jha,
``Vibration-based secure side channel for medical devices,"
*IEEE Design Automation Conference*, June 2015. - D. Bhattacharya, R. V. Joshi, H. A. Ainspan, N. D. Sathaye, M.
Bajaj, S. Gundapaneni, and N. K. Jha, ``TCAD structure synthesis and
capacitance extraction of a voltage-controlled oscillator using
automated layout-to-device synthesis methodology,"
*IEEE Custom Integrated Circuits Conference*, Aug. 2014. - S. Chaudhuri and N. K. Jha, ``FinFET logic circuit optimization
with different FinFET styles: Lower power possible at higher supply
voltage,"
*IEEE Int. Conf. on VLSI Design*, Jan. 2014. - M. Zhang, A. Raghunathan, and N. K. Jha, ``Towards
trustworthy medical devices and body area networks,"
*IEEE Design Automation Conference*, June 2013 (Invited paper). - S. Basuroy, J. W. Chuah, and N. K. Jha, ``Making buildings
energy-efficient through retrofits: A survey of available technologies,"
*IEEE Power and Energy Society General Meeting*, June 2013. - M. Zhang, M. M. Kermani, A. Raghunathan, and N. K. Jha,
``Energy-efficient and secure sensor data transmission using encompression,"
*IEEE Int. Conf. on VLSI Design*, Jan. 2013. - Y. Yang and N. K. Jha, ``FinPrin: Analysis and optimization of FinFET
logic circuits under PVT variations,"
*IEEE Int. Conf. on VLSI Design*, Jan. 2013. - J.-W. Chuah, C. Li, A. Raghunathan, and N. K. Jha, ``Localized heating
for building energy efficiency,"
*IEEE Int. Conf. on VLSI Design*, Jan. 2013. - M. M. Kermani, M. Zhang, A. Raghunathan, and N. K. Jha, ``Emerging
frontiers in embedded security,"
*IEEE Int. Conf. on VLSI Design*, Jan. 2013. - M. Shoaib, N. K. Jha, and N. Verma, ``A compressed-domain
processor for seizure detection to simultaneously reduce computation and
communication energy,"
*IEEE Custom Integrated Circuits Conference*, Aug. 2012. - A. Chakrabarti, C. Lin, and N. K. Jha, ``Design of quantum
circuits for random walk algorithms,"
*IEEE Annual Symp. on VLSI*, Aug. 2012. - M. Shoaib, N. K. Jha, and N. Verma, ``Enabling advanced inference
on sensor nodes through direct use of compressively-sensed signals,"
*IEEE Design Automation and Test in Europe Conf.*, Mar. 2012. - S. Chaudhuri, P. Mishra, and N. K. Jha, ``Accurate leakage
estimation for FinFET standard cells using the response surface
methodology,"
*IEEE Int. Conf. on VLSI Design*, Jan. 2012. - A. Bhoj, R. V. Joshi,
S. Polonsky, R. Kanj, S. Saroop, Y. Tan, and N. K. Jha, ``Hardware-assisted 3D
TCAD predictive capacitance extraction in 32nm SOI SRAMs,"
*IEEE Int. Electronic Devices Meeting*, Dec. 2011. - S. Chaudhuri and
N. K. Jha, ``3D vs. 2D analysis of FinFET logic gates under process
variations,"
*IEEE/ACM Int. Conf. on Computer Design*, Oct. 2011. - M. Shoaib, N. K. Jha,
and N. Verma, ``Subthreshold computational circuits for high-order data-driven
analysis of physiological signals,"
*Subthreshold Microelectronics Conf.*, Sept. 2011. - C. Li, A. Raghunathan,
and N. K. Jha, ``Hijacking an insulin pump: Security attacks and defenses for
a diabetes therapy system,"
*IEEE Int. Conf. on e-Health Networking Applications and Services*, June 2011. - M. Shoaib, N. K. Jha,
and N. Verma, ``A low-energy computation platform for data-driven biomedical
monitoring algorithms,"
*IEEE Design Automation Conf.*, June 2011. - C.-Y. Lee and N. K. Jha,
``CACTI-FinFET: An integrated delay and power modeling framework for
FinFET-based caches under process variations,"
*IEEE Design Automation Conf.*, June 2011. - A. Bhoj and N. K. Jha,
``Design of ultralow-leakage logic gates in high-performance FinFET
technology,"
*IEEE Int. Symp. on Quality Electronic Design*Mar. 2011 (Invited Paper). - J.-W. Chuah,
A. Raghunathan, and N. K. Jha, ``An evaluation of energy-saving
technologies for residential purposes,"
*IEEE Power Engineering Society General Meeting*, July 2010. - C. Li,
A. Raghunathan, and N. K. Jha, ``Secure virtual machine execution under
an untrusted management OS,"
*IEEE International Conference on Cloud Computing*, July 2010. - C. Li,
A. Raghunathan, and N. K. Jha, ``A secure user interface
for web applications running under an untrusted operating system,"
*IEEE International Conference on Computer and Information Technology*, June 2010. - M. O. Simsir
and N. K. Jha, ``NanoV: Nanowire-based VLSI design,"
*IEEE International Symposium on Nanoscale Architectures*, June 2010. - M. O. Simsir,
A. Bhoj, and N. K. Jha, ``Fault modeling for FinFET
circuits,"
*IEEE International Symposium on Nanoscale Architectures*, June 2010. - M. Turi, J. Delgado-Frias, and N. K. Jha, ``Low-power FinFET
design schemes for NOR address decoders,"
*IEEE International Symposium on VLSI Design, Automation and Test*, Apr. 2010. - P. Mishra and
N. K. Jha, ``Low-power FinFET circuit synthesis using surface orientation
optimization,"
*IEEE Design Automation and Test in Europe Conference*, Mar. 2010. - P. Mishra, A. Bhoj,
and N. K. Jha, ``Die-level leakage power analysis of FinFET circuits
considering process variations,"
*IEEE Int. Symp. on Quality Electronic Design*, Mar. 2010. - N. Agarwal, L.-S. Peh,
and N. K. Jha, ``In-network coherence filtering: Snoopy coherence without
broadcasts,"
*IEEE Int. Symp. on Microarchitecture*, Dec. 2009. - M. Simsir and N. K. Jha,
``Thermal characterization of BIST, scan design and sequential test
methodologies,"
*IEEE Int. Test Conf.*, Nov. 2009. - A. Bhoj and N. K. Jha,
``Pragmatic design of gated-diode FinFET DRAMs,"
*IEEE Int. Conf. on Computer Design*, Oct. 2009. - C.-Y. Lee and N. K. Jha,
``FinFET-based dynamic power management of on-chip interconnection networks
through adaptive back-gate biasing,"
*IEEE Int. Conf. on Computer Design*, Oct. 2009. - N. Agarwal, T. Krishna,
L.-S. Peh, and N. K. Jha, `` GARNET: A detailed on -chip network model
inside a full-system simulator,"
*IEEE Int. Symp. on Performance Analysis of Systems and Software*, Apr. 2009. - C. Li, A. Raghunathan,
and N. K. Jha, ``An architecture for secure software defined radio,"
*IEEE Design Automation and Test in Europe Conf.*, Mar. 2009. - N. Agrawal, L.-S. Peh,
and N. K. Jha, ``In-network snoop ordering (INSO): Snoopy coherence on
unordered interconnects,"
*IEEE Int. Symp. on High-Performance Computer Architecture*, Feb. 2009. - A. Kumar, L.-S. Peh, and
N. K. Jha, ``Token flow control,"
*IEEE Int. Symp. on Microarchitecture*, Oct. 2008. - N. Aaraj, A. Raghunathan,
and N. K. Jha, ``Dynamic binary instrumentation based framework for malware
(virus) defense,"
*Conf. on Detection of Intrusions and Malware and Vulnerability Assessment*, July 2008. - P. Mishra, A. Muttreja,
and N. K. Jha, ``Evaluation of multiple supply and threshold voltages for
low-power finFET circuit synthesis,"
*IEEE/ACM Int. Symp. on Nanoscale Architectures*, June 2008. - A. Kumar, N. Agarwal, L.-S. Peh, and N. K. Jha, ``A system-level
perspective for efficient NoC design,"
*IEEE Int. Parallel and Distributed Processing Symposium*, Apr. 2008. - A. Muttreja, S. Ravi,
and N. K. Jha, ``Variability-tolerant register-transfer level synthesis,"
*Int. Conf. on VLSI Design*, Jan. 2008. - M. Simsir, S. Cadambi, F. Ivancic,
M. Roetteler, and N. K. Jha, ``Fault-tolerant computing using a hybrid nano-CMOS
architecture,"
*Int. Conf. on VLSI Design*, Jan. 2008. - A. Muttreja, P. Mishra, and
N. K. Jha, ``Threshold voltage control through multiple supply voltages for power-efficient
FinFET interconnects,"
*Int. Conf. on VLSI Design*, Jan. 2008. - A. Muttreja, N. Agrawal,
and N. K. Jha, ``CMOS logic design with independent-gate FinFETs,"
*IEEE Int. Conf. on Computer Design*, Oct. 2007. - A. Kumar, P. Kundu, L.-S. Peh,
and N. K. Jha, ``A 920Gbits/s 3.6GHz single-cycle NoC router with a novel switch
allocator in 65nm CMOS,"
*IEEE Int. Conf. on Computer Design*, Oct. 2007. - A. Kumar, L.-S. Peh, P. Kundu, and
N. K. Jha, ``Express virtual channels: Towards the ideal on-chip interconnection fabric,"
*Int. Symposium on Computer Architecture*, June 2007. - W. Zhang, L. Shang, and N. K. Jha,
``NanoMap: An integrated design optimization flow for a hybrid nanotube/CMOS dynamically
reconfigurable architecture,"
*IEEE Design Automation Conference*, June 2007. - L. Yan, L. Zhong, and N. K. Jha, ``Energy comparison and optimization of
wireless body-area network technologies,"
*Int. Conf. on Body Area Networks*, June 2007. - N. Aaraj, A. Raghunathan, S. Ravi,
and N. K. Jha, ``Energy and execution time analysis of a software-based trusted
platform module,"
*IEEE Design Automation and Test in Europe Conf.*, Apr. 2007. - L. Lingappan, V. Gangaram,
N. K. Jha, and S. Chakravarty, ``Fast enhancement of validation test sets to
improve stuck-at fault coverage,"
*Int. Conf. on VLSI Design*, Jan. 2007. - D. Arora, A. Raghunathan,
S. Ravi, and N. K. Jha, ``Architectural support for safe software execution on
embedded processors,"
*IEEE Hardware/Software Co-Design Symp./Int. Symp. on System Synthesis*, Oct. 2006. - A. Muttreja,
A. Raghunathan, S. Ravi, and N. K. Jha, ``Active learning driven data
acquisition for sensor networks,"
*IEEE Symposium on Computers and Communications*, June 2006. - W. Zhang, N. K. Jha,
and L. Shang, ``NATURE: A CMOS/nanotube hybrid reconfigurable architecture,"
*IEEE Design Automation Conference*, June 2006. - D. Arora, S. Ravi,
A. Raghunathan, M. Sankaradass, N. K. Jha, and S. Chakradhar,
``Software architecture exploration for high-performance security processing
on a multiprocessor mobile SoC,"
*IEEE Design Automation Conference*, June 2006. - A. Kumar, L.-S. Peh,
L. Shang, and N. K. Jha, ``HybDTM: A coordinated hardware-software approach
for dynamic thermal management,"
*IEEE Design Automation Conference*, June 2006. - R. Zhang and N. K. Jha,
``Threshold/majority logic synthesis and concurrent error detection
targeting nanoelectronic implementations,"
*IEEE/ACM Great Lakes Symposium on VLSI*, Apr. 2006. - N. Potlapally,
A. Raghunathan, S. Ravi, N. K. Jha, and R. B. Lee, ``Satisfiability-based
side-channel attacks on software implementations of cryptographic algorithms,"
*IEEE Design Automation and Test in Europe Conf.*, Mar. 2006. - P. Gupta, N. K. Jha, and
L. Lingappan, ``Test generation for combinational quantum cellular automata
(QCA) circuits,"
*IEEE Design Automation and Test in Europe Conf.*, Mar. 2006. - N. Aaraj, A. Raghunathan,
S. Ravi, and N. K. Jha, ``Architectures for efficient face authentication
in embedded systems,"
*IEEE Design Automation and Test in Europe Conf.*, Mar. 2006. - R. Zhang and N. K. Jha,
``State encoding of finite-state machines targeting threshold and majority
logic based implementations with application to nanotechnologies,"
*Int. Conf. on VLSI Design*, Jan. 2006. - N. Potlapally, S. Ravi,
A. Raghunathan, R. B. Lee, and N. K. Jha, ``Impact of configurability and
extensibility on IPSec protocol execution on embedded processors,"
*Int. Conf. on VLSI Design*, Jan. 2006. - F. Sun, S. Ravi,
A. Raghunathan, and N. K. Jha, ``Hybrid custom instruction and co-processor
synthesis methodology for extensible processors,"
*Int. Conf. on VLSI Design*, Jan. 2006. - L. Lingappan and
N. K. Jha, ``Improving the performance of automatic sequential test generation
by targeting hard-to-test faults,"
*Int. Conf. on VLSI Design*, Jan. 2006. - L. Yan, L. Zhong, and
N. K. Jha, ``Towards a responsive, yet power-efficient, operating system:
A holistic approach,"
*IEEE/ACM Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems*, Oct. 2005. - W. Zhang and N. K. Jha,
``ALLCN: An automatic logic-to-layout tool for carbon nanotube based
nanotechnology,"
*IEEE Int. Conf. on Computer Design*, Oct. 2005. - D. Arora, S. Ravi,
A. Raghunathan, and N. K. Jha, ``Enhancing security through hardware-assisted
run-time validation of program data properties,"
*IEEE Hardware/Software Co-Design Symp./Int. Symp. on System Synthesis*, Oct. 2005. - C. Huang, S. Ravi,
A. Raghunathan, and N. K. Jha, ``Eliminating memory bottlenecks for a
JPEG encoder through distributed logic-memory architecture and
computation-unit integrated memory,"
*IEEE Custom Integrated Circuit Conf.*, Sept. 2005. - L. Zhong, M. Sinclair,
and N. K. Jha, ``A personal-area network of low-power wireless interfacing
devices for handhelds: System and hardware design,"
*IEEE Mobile HCI*, Sept. 2005. - A. Muttreja, S. Ravi,
A. Raghunathan, and N. K. Jha, ``Hybrid simulation for embedded software
energy estimation,"
*IEEE Design Automation Conf.*, June 2005. - L. Yan, L. Zhong, and
N. K. Jha, ``User-perceived latency driven voltage scaling for interactive
applications,"
*IEEE Design Automation Conf.*, June 2005. - P. Gupta, S. Ravi,
A. Raghunathan, and N. K. Jha, ``Efficient and secure fingerprint-based
user authentication for embedded systems,"
*IEEE Design Automation Conference*, June 2005. - L. Zhong and N. K. Jha,
``Energy efficiency of handheld computer interfaces: Limits, characterization
and practice,"
*USENIX/ACM MobiSys*, May 2005. - L. Lingappan and
N. K. Jha, ``Unsatisfiability based efficient design for testability solution
for register-transfer level circuits,"
*IEEE VLSI Test Symp.*, Apr. 2005. - D. Arora, S. Ravi,
A. Raghunathan, and N. K. Jha, ``Secure embedded processing through
hardware-assisted run-time monitoring,"
*IEEE Design Automation and Test in Europe Conf.*, Feb. 2005. - L. Lingappan,
S. Ravi, A. Raghunathan, N. K. Jha, and S. Chakradhar, ``A flexible
system-level test architecture for compressed test delivery,"
*Int. Conf. on VLSI Design*, Jan. 2005. - R. Zhang, P. Gupta,
and N. K. Jha, ``Synthesis of majority networks for QCA-based logical
devices,"
*Int. Conf. on VLSI Design*, Jan. 2005. - F. Sun, S. Ravi,
A. Raghunathan, and N. K. Jha, ``Synthesis of application-specific
heterogeneous multiprocessor architectures using extensible processors,"
*Int. Conf. on VLSI Design*, Jan. 2005. - L. Shang, L.-S. Peh,
A. Kumar, and N. K. Jha, ``Thermal modeling, characterization and management
of on-chip interconnection networks,"
*IEEE Int. Symp. on Microarchitecture*, Nov. 2004. - C. Huang, S. Ravi,
A. Raghunathan, and N. K. Jha, ``High-level synthesis using computation-unit
integrated memories,"
*IEEE Int. Conf. on Computer-Aided Design*, Nov. 2004. - L. Zhong,
A. Raghunathan, S. Ravi, N. K. Jha, and S. Chakradhar, ``Power estimation for
cycle-accurate functional descriptions of hardware,"
*IEEE Int. Conf. on Computer-Aided Design*, Nov. 2004. - P. Gupta, R. Zhang, and
N. K. Jha, ``An automatic test pattern generation framework for combinational
threshold logic networks,"
*IEEE Int. Conf. on Computer Design*, Oct. 2004. - Y. Fei, L. Zhong, and
N. K. Jha, ``An energy-aware framework for coordinated dynamic software
management in mobile computers,"
*IEEE/ACM Int. Symp. on Modeling, Analysis and Simulation of Computer and Telecommunication Systems*, Oct. 2004. - T. K. Tan,
A. Raghunathan, and N. K. Jha, ``An energy-aware synthesis methodology for
OS-driven multi-process embedded software,"
*Int. Conf. on Embedded Systems and Applications*, June 2004. - K. Vallerio,
L. Zhong, and N. K. Jha, ``Energy-efficient graphical user interface design,"
*Int. Conf. Pervasive Computing and Communications*, June 2004. - A. Muttreja, S.
Ravi, A. Raghunathan, and N. K. Jha, ``Automated performance/energy
macromodeling of embedded software,"
*IEEE Design Automation Conf.*, June 2004. - K. Vallerio and
N. K. Jha, ``Language selection for mobile systems: Java, C or both,"
*Int. Conf. on Embedded Systems and Applications*, June 2004. - K. Vallerio and
N. K. Jha, ``Evaluating conditional statements in embedded system software:
Systematic methodologies for reducing energy consumption,"
*Int. Conf. on Embedded Systems and Applications*, June 2004. - P. Gupta and N. K. Jha,
``An algorithm for nano-pipelining of circuits and architectures for nanotechnologies,"
*IEEE Design Automation and Test in Europe Conf.*, Feb. 2004. - R. Zhang, P. Gupta, L. Zhong,
and N. K. Jha, ``Synthesis and optimization of threshold logic networks with application
to nanotechnologies,"
*Design Automation and Test in Europe Conf.*, Feb. 2004. - A. Agrawal and N. K. Jha, ``Synthesis of reversible logic,"
*Design Automation and Test in Europe Conf.*, Feb. 2004. - W. Wang, A. Raghunathan, and N. K. Jha, ``Profiling
driven computation reuse: An embedded software synthesis technique
for energy and performance optimization,"
*Int. Conf. on VLSI Design*, Jan. 2004. - L. Zhong and N. K. Jha,
``Dynamic power optimization for interactive systems,"
*Int. Conf. on VLSI Design*, Jan. 2004. - Y. Fei, S. Ravi, A. Raghunathan,
and N. K. Jha, ``Energy-optimizing source code transformations for OS-driven embedded
software,"
*Int. Conf. on VLSI Design*, Jan. 2004. - L. Zhong and N. K. Jha,
``Graphical user interface energy characterization for hendheld computers,"
*Int. Conf. on Compilers, Architecture and Synthesis for Embedded Systems*, Nov. 2003. - F. Sun, A. Raghunathan,
S. Ravi, and N. K. Jha, ``A scalable application-specific processor synthesis
methodology,"
*IEEE Int. Conf. on Computer-Aided Design*, Nov. 2003. - C. Huang, S. Ravi,
A. Raghunathan, and N. K. Jha, ``Synthesis of distributed
heterogeneous architectures for memory-intensive applications,"
*IEEE Int. Conf. on Computer-Aided Design*, Nov. 2003. - P. Gupta, L. Zhong, and
N. K. Jha, ``A high-level interconnect power model
for design space exploration,"
*IEEE Int. Conf. on Computer-Aided Design*, Nov. 2003. - L. Yan, J. Luo, N. K. Jha,
``Combined dynamic voltage scaling and adaptive
body biasing for heterogeneous distributed real-time embedded systems,"
*IEEE Int. Conf. on Computer-Aided Design*, Nov. 2003. - L. Lingappan, S. Ravi, and
N. K. Jha, ``Test generation for non-separable
RTL controller-datapath circuits using a satisfiability based approach,"
*IEEE Int. Conf. on Computer Design*, Sept. 2003. - N. R. Potlapally,
S. Ravi, A. Raghunathan, and N. K. Jha,
``Analyzing the energy consumption of security protocols,''
*IEEE Int. Symp. on Low Power Electronics and Design*, Aug. 2003. - L. Shang, L-S. Peh,
and N. K. Jha, ``PowerHerd: Dynamic satisfaction
of peak power constraints in interconnection networks,"
*IEEE Int. Conf. on Supercomputing*, June 2003. - W. Wang,
T. K. Tan, J. Luo, Y. Fei, L. Shang, K. S. Vallerio,
L. Zhong, A. Raghunathan, and N. K. Jha, ``A comprehensive high-level
synthesis system for control-flow intensive behaviors for low power,''
*IEEE Great Lakes VLSI Symposium*, Apr. 2003. - T. K. Tan, A.
Raghunathan, and N. K. Jha, ``Software architectural
transformations: A new approach to low energy embedded software,''
*IEEE Design Automation and Test in Europe Conf.*, Mar. 2003. - Y. Fei, S. Ravi,
A. Raghunathan, and N. K. Jha, ``Energy estimation for extensible
processors,''
*IEEE Design Automation and Test in Europe Conf.*, Mar. 2003. - J. Luo, L.-S. Peh, and N. K. Jha, ``Simultaneous dynamic voltage
scaling of processors and communication links in real-time distributed
embedded systems,''
*IEEE Design Automation and Test in Europe Conf.*, Mar. 2003. - L. Shang, L.-S. Peh,
and N. K. Jha, ``Dynamic voltage scaling with links
for power optimization of interconnection networks,''
*IEEE High-Performance Computer Architecture Symposium*, Jan. 2003. - J. Luo and N. K. Jha,
``Power-profile driven variable voltage scaling
for heterogeneous distributed real-time embedded systems,''
*Int. Conf. on VLSI Design*, Jan. 2003. - K. Vallerio and N. K. Jha,
``Task graph extraction for embedded
system synthesis,''
*Int. Conf. on VLSI Design*, Jan. 2003. - W. Wang, A. Raghunathan,
N. K. Jha, and S. Dey, ``High-level
synthesis of multi-process behavioral descriptions,''
*Int. Conf. on VLSI Design*, Jan. 2003 (Best Paper Award). - J. Luo and N. K. Jha,
``Low power distributed embedded systems: Dynamic
voltage scaling and synthesis,''
*Int. Conf. on High-Performance Computing*, Dec. 2002 (invited paper). - F. Sun, S. Ravi,
A. Raghunathan, and N. K. Jha, ``Synthesis of custom processors
based on extensible platforms,''
*IEEE Int. Conf. on Computer-Aided Design*, Nov. 2002. - C. Huang, S. Ravi,
A. Raghunathan, and N. K. Jha, ``High-level synthesis of
distributed logic-memory architectures,''
*IEEE Int. Conf. on Computer-Aided Design*, Nov. 2002. - L. Zhong and N. K. Jha,
``Interconnect-aware high-level synthesis for low
power,''
*IEEE Int. Conf. on Computer-Aided Design*, Nov. 2002. - L. Shang, R. Dick, and
N. K. Jha, ``An economics-based power-aware protocol
for computation distribution in mobile ad-hoc networks,''
*Fourteenth IASTED Int. Conf. on Parallel and Distributed Computing and Systems*, Nov. 2002 (Best Paper Award). - L. Zhong, J. Luo, Y. Fei, and
N. K. Jha, ``Register binding based
power management for high-level synthesis of control-flow intensive
behaviors,''
*IEEE Int. Conf. on Computer Design*, Sept. 2002. - T. K. Tan, A. Raghunathan,
and N. K. Jha, ``Embedded operating system energy
analysis and macro-modeling,''
*IEEE Int. Conf. on Computer Design*, Sept. 2002. - T. K. Tan,
A. Raghunathan, and N. K. Jha, ``EMSIM: An energy simulation
framework for an embedded operating system,''
*Int. Conf. on Circuits & Systems*, May 2002. - K. Vallerio and
N. K. Jha, ``Task graph transformation to aid system synthesis,''
*Int. Conf. on Circuits & Systems*, May 2002. - L. Shang and N. K. Jha,
``Hardware-software co-synthesis of low power
real-time distributed embedded systems using dynamically reconfigurable FPGAs,''
*Int. Conf. on VLSI Design*, Jan. 2002. - Y. Fei and N. K. Jha,
``Functional partitioning for low power distributed systems of systems-on-a-chip,''
*Int. Conf. on VLSI Design*, Jan. 2002. - J. Luo and N. K. Jha,
``Static and dynamic variable voltage scheduling
algorithms for real-time heterogeneous distributed embedded systems,''
*Int. Conf. on VLSI Design*, Jan. 2002. - W. Wang, A. Raghunathan,
G. Lakshminarayana, and N. K. Jha, ``Input space adaptive software synthesis for
energy and performance optimization,''
*Int. Conf. on VLSI Design*, Jan. 2002. - N. K. Jha, ``Low power system scheduling and synthesis,''
*IEEE Int. Conf. on Computer-Aided Design*, Nov. 2001 (invited paper). - S. Ravi and N. K. Jha,
``Fast test generation for circuits with RTL and
gate-level views,''
*IEEE Int. Test Conf.*, Oct. 2001. - L. Shang and N. K. Jha,
``High-level power modeling of CPLDs and FPGAs,''
*IEEE Int. Conf. on Computer Design*, Sept. 2001. - T. K. Tan, A. Raghunathan,
G. Lakshminarayana, and N. K. Jha, ``High-level software energy macro-modeling,''
*IEEE Design Automation Conf.*, June 2001. - J. Luo and N. K. Jha,
``Battery-aware static scheduling for distributed
real-time embedded systems,''
*IEEE Design Automation Conf.*, June 2001. - W. Wang, A. Raghunathan,
G. Lakshminarayana, and N. K. Jha, ``Input space adaptive design: A high-level
methodology for energy and performance optimization,''
*IEEE Design Automation Conf.*, June 2001. - S. Ravi and N. K. Jha,
``Synthesis of system-on-a-chip for testability,''
*Int. Conf. on VLSI Design*, Jan. 2001. - J. Luo and N. K. Jha,
``Power-conscious joint scheduling of periodic
task graphs and aperiodic tasks in distributed real-time embedded systems,''
*IEEE Int. Conf. on Computer-Aided Design*, Nov. 2000. - S. Ravi, G. Lakshminarayana,
and N. K. Jha, ``Reducing test application
time in high-level test generation,''
*IEEE Int. Test Conf.*, Oct. 2000. - K. S. Khouri and
N. K. Jha, ``Leakage power analysis and reduction
during behavioral synthesis,''
*IEEE Int. Conf. on Computer Design*, Sept. 2000. - S. Ravi, I. Ghosh, V. Boppana,
and N. K. Jha, ``A technique for
identifying RTL and gate-level correspondences,''
*IEEE Int. Conf. on Computer Design*, Sept. 2000. - R. P. Dick, G. Lakshminarayana,
A. Raghunathan, and N. K. Jha, ``Power analysis of embedded operating systems,''
*IEEE Design Automation Conf.*, June 2000. - R. P. Dick and N. K. Jha,
``A survey of Princeton tools for automatic
synthesis of low power embedded systems,''
*Power Sources Conf.*, Apr. 2000. - R. P. Dick and N. K.
Jha, ``COWLS: Hardware-software co-synthesis
of distributed wireless low-power embedded client-server systems,''
*Int. Conf. on VLSI Design*, Jan. 2000. - K. S. Khouri and
N. K. Jha, ``Clock selection for performance
optimization of control-flow intensive behaviors,''
*Int. Conf. on VLSI Design*, Jan. 2000. - S. Ravi, G.
Lakshminarayana, and N. K. Jha, ``A framework for testing
core-based systems-on-a-chip,''
*IEEE Int. Conf. on Computer-Aided Design*, Nov. 1999. - K. S. Khouri, G.
Lakshminarayana, and N. K. Jha, ``Memory binding
for performance optimization of control-flow intensive behaviors,''
*IEEE Int. Conf. on Computer-Aided Design*, Nov. 1999. - G. Lakshminarayana, A.
Raghunathan, K. S. Khouri, and N. K. Jha,
``Common case computation: A high-level power-optimizing technique,''
*IEEE Design Automation Conf.*, June 1999 (Best Paper Award). - S. Ravi, G.
Lakshminarayana, and N. K. Jha, ``TAO-BIST: A framework for testability
analysis and optimization of RTL circuits using BIST,''
*VLSI Test Symp.*, Apr. 1999. - R. P. Dick and N. K.
Jha, ``MOCSYN: Multiobjective core-based single-chip system synthesis,''
*Design Automation and Test in Europe Conf.*, Feb. 1999. - R. P. Dick and N. K. Jha,
``CORDS: Hardware-software co-synthesis of reconfigurable real-time
distributed embedded systems,''
*IEEE Int. Conf. on Computer-Aided Design*, Nov. 1998. - G. Lakshminarayana, A.
Raghunathan, N. K. Jha and S. Dey, ``Transforming
control-flow intensive designs to facilitate power management,''
*IEEE Int. Conf. on Computer-Aided Design*, Nov. 1998. - S. Ravi, G.
Lakshminarayana, and N. K. Jha, ``Removal of memory access bottlenecks for
scheduling control-flow intensive behavioral descriptions,''
*IEEE Int. Conf. on Computer-Aided Design*, Nov. 1998. - S. Ravi, G. Lakshminarayana, and N. K. Jha, ``TAO: Regular expression
based high-level testability analysis and optimization,''
*IEEE International Test Conf.*, Oct. 1998. - K. S. Khouri, G. Lakshminarayana and N. K. Jha, ``Fast high-level power
estimation for control-flow intensive designs,''
*IEEE Int. Symp. on Low Power Electronics and Design*, Aug. 1998. - I. Ghosh, S. Dey, and N. K. Jha, ``A fast and low cost testing technique
for core-based system-on-a-chip,''
*IEEE Design Automation Conf.*, June 1998. - I. Ghosh, N. K. Jha, and S. Bhawmik, ``A BIST scheme for RTL
controller-data paths based on symbolic testability analysis,''
*IEEE Design Automation Conf.*, June 1998. - G. Lakshminarayana and N. K. Jha, ``Synthesis of power-optimized
and area-optimized circuits from hierarchical behavioral descriptions,''
*IEEE Design Automation Conf.*, June 1998. - G. Lakshminarayana, A. Raghunathan, and N. K. Jha, ``Incorporating
speculative execution into scheduling of control-flow intensive behavioral
descriptions,''
*IEEE Design Automation Conf.*, June 1998. - G. Lakshminarayana and N. K. Jha,
``FACT: A framework for the
application of throughput and power-optimizing transformations to control-flow
intensive behavioral descriptions,''
*IEEE Design Automation Conf.*, June 1998. - K. S. Khouri, G. Lakshminarayana and N. K. Jha, ``IMPACT: A high-level
synthesis system for low power control-flow intensive circuits,''
*Design Automation and Test in Europe Conf.*, Feb. 1998. - B. Dave and N. K. Jha, ``CASPER: Concurrent hardware-software
co-synthesis of hard real-time aperiodic and periodic specifications of
embedded system architectures,''
*Design Automation and Test in Europe Conf.*, Feb. 1998. - B. Dave and N. K. Jha, ``COHRA: Hardware-software co-synthesis of
hierarchical distributed embedded system architectures,''
*Int. Conf. on VLSI Design*, Chennai, India, Jan. 1998. - G. Lakshminarayana,
A. Raghunathan, N. K. Jha and S. Dey, ``Power management
in high-level synthesis,''
*Int. Conf. on VLSI Design*, Chennai, India, Jan. 1998 (Best Paper Award). - I. Ghosh, N. K. Jha and S. Dey, ``A low overhead design for testability
and test generation technique for core-based systems,''
*IEEE Int. Test Conf.*, Washington, D.C., Nov. 1997. - R. P. Dick, and N. K.
Jha, ``MOGAC: A multiobjective genetic algorithm for the co-synthesis of
hardware-software embedded systems,''
*IEEE Int. Conf. on Computer-Aided Design*, San Jose, Nov. 1997. - G. Lakshminarayana, K. S. Khouri and N. K. Jha,
``Wavesched: A novel
scheduling technique for control-flow intensive behavioral descriptions,''
*IEEE Int. Conf. on Computer-Aided Design*, San Jose, Nov. 1997. - I. Ghosh, A. Raghunathan,
and N. K. Jha, ``Hierarchical test generation and design for testability
of ASPPs and ASIPs,''
*IEEE Design Automation Conf.*, Anaheim, June 1997. - B. Dave, G. Lakshminarayana and N. K. Jha, ``COSYN: Hardware-software
co-synthesis of embedded systems,''
*IEEE Design Automation Conf.*, Anaheim, June 1997. - A. Raghunathan, S. Dey, N. K. Jha and K. Wakabayashi, ``Power management
techniques for control-flow intensive designs,''
*IEEE Design Automation Conf.*, Anaheim, June 1997. - B. Dave and N. K. Jha, ``COFTA: Hardware-software co-synthesis of
heterogeneous distributed embedded system architectures for low overhead
fault tolerance,''
*IEEE Int. Symp. on Fault-Tolerant Computing*, Seattle, June 1997 (Best Paper Award). - A. Raghunathan, S. Dey and N. K. Jha, ``Register transfer level
estimation of switching activity and power consumption,''
*IEEE Int. Conf. on Computer-Aided Design*, Nov. 1996. - I. Ghosh, A. Raghunathan, and N. K. Jha, ``A design for testability
technique for RTL circuits using control/data flow extraction,''
*IEEE Int. Conf. on Computer-Aided Design*, Nov. 1996. - A. Raghunathan, S. Dey, N. K. Jha and K. Wakabayashi, ``Controller
re-specification to minimize switching activity in controller/data path
circuits,''
*Int. Symp. on Low Power Electronics & Design*, Aug. 1996. - G. Lakshminarayana, A. Raghunathan, and N. K. Jha, ``Behavioral synthesis
of fault secure controller/datapaths using aliasing probability analysis,''
*IEEE Int. Symp. on Fault-Tolerant Computing*, June 1996. - A. Raghunathan, S. Dey and N. K. Jha, ``Register transfer level
power optimization techniques with emphasis on glitch analysis and reduction,''
*IEEE Design Automation Conf.*, June 1996. - A. Raghunathan and N. K. Jha, ``An iterative improvement algorithm for
low power data path synthesis,''
*IEEE Int. Conf. on Computer-Aided Design*, Santa Clara, Nov. 1995. - I. Ghosh, A. Raghunathan, and N. K. Jha, ``Design for hierarchical testability of RTL circuits
obtained by behavioral synthesis,''
*IEEE Int. Conf. on Computer Design*, Austin, Oct. 1995. - S. Srinivasan and N. K. Jha, ``CRAFT: Criticality based fault tolerance
for real-time distributed systems with resource constraints,''
*Int. Conf. on Parallel and Distributed Computing Systems*, Orlando, Sept. 1995. - S. Srinivasan and N. K. Jha, ``Hardware-software co-synthesis of
fault-tolerant real-time distributed embedded systems,''
*European Design Automation Conf.*, Brighton, U.K., Sept. 1995. - S. Srinivasan and N. K. Jha, ``Task allocation for reliability and
safety in distributed systems,''
*Int. Conf. on Parallel Proc.*, Oconomowoc, Aug. 1995. - A. Raghunathan and N. K. Jha, ``An ILP formulation for low power based on
minimizing switched capacitance during data path allocation,''
*IEEE Int. Symp. on Circuits & Systems*, Seattle, May 1995. - S. M. Nowick, N. K. Jha and F.-C. Cheng, ``Synthesis of asynchronous
circuits for stuck-at and robust path delay fault testability,''
*Int. Conf. on VLSI Design*, New Delhi, Jan. 1995. - S. Yajnik, S. Srinivasan and N. K. Jha, ``TBFT: A task-based fault
tolerance scheme for distributed systems,''
*Int. Conf. on Parallel & Distributed Computing Systems*, Las Vegas, Oct. 1994. - A. Raghunathan and N. K. Jha, ``Behavioral synthesis for low power,''
*IEEE Int. Conf. on Computer Design*, Cambridge, Oct. 1994. - S. Bhatia and N. K. Jha, ``Behavioral synthesis for hierarchical
testability of controller/data path circuits with conditional branches,''
*IEEE Int. Conf. on Computer Design*, Cambridge, Oct. 1994. - S. Yajnik and N. K. Jha, ``Graceful degradation in algorithm-based fault
tolerant multiprocessor systems,''
*IEEE Int. Symp. on Circuits & Systems*, London, May 1994. - S. Yajnik and N. K. Jha, ``Synthesis of fault-tolerant architectures
for molecular dynamics,''
*IEEE Int. Symp. on Circuits & Systems*, London, May 1994. - S. Bhatia and N. K. Jha, ``Genesis: A behavioral synthesis system for
hierarchical testability,''
*The European Design & Test Conf.*, Paris, Feb. 1994. - S. Yajnik and N. K. Jha, ``Analysis and randomized design of
algorithm-based fault tolerant multiprocessor systems under the extended
graph-theoretic model,''
*ISCA Int. Conf. on Parallel & Distributed Systems*, Louisville, Oct. 1993. - T.-C. Lee, N. K. Jha and W. H. Wolf, ``A conditional resource sharing
method for behavioral synthesis of highly testable data paths,''
*IEEE Int. Test Conf.*, Baltimore, Oct. 1993. - S. Srinivasan and N. K. Jha, ``Efficient diagnosis in algorithm-based
fault tolerant multiprocessor systems,''
*IEEE Int. Conf. on Computer Design*, Boston, Oct. 1993. - S. Bhatia and N. K. Jha, ``Synthesis of sequential circuits for easy
testability through a performance-oriented parallel partial scan,''
*IEEE Int. Conf. on Computer Design*, Boston, Oct. 1993 (Best Paper Award). - S. Yajnik and N. K. Jha, ``Design of algorithm-based fault tolerant
multiprocessor systems with in-system checks,''
*Int. Conf. on Parallel Processing*, St. Charles, IL, Aug. 1993. - T.-C. Lee, N. K. Jha, and W. H. Wolf, ``Behavioral synthesis of highly
testable data paths under the non-scan and partial scan environments,''
*IEEE Design Automation Conf.*, Dallas, June 1993. - S. Bhatia and N. K. Jha, ``Synthesis of sequential circuits for
robust path delay fault testability,''
*Int. Conf. on VLSI Design*, Bombay, India, Jan. 1993. - T.-C. Lee, W. H. Wolf, and N. K. Jha, ``Behavioral synthesis for easy
testability in data path scheduling,''
*IEEE Int. Conf. on Computer-Aided Design*, Santa Clara, Nov. 1992. - N. K. Jha, S.-J. Wang and P. C. Gripka, ``Multiple input bridging fault
detection in CMOS sequential circuits,''
*IEEE Int. Conf. on Computer Design*, Boston, Oct. 1992. - T.-C. Lee, W. H. Wolf, N. K. Jha, and J. M. Acken, ``Behavioral synthesis
for easy testability in data path allocation,''
*IEEE Int. Conf. on Computer Design*, Boston, Oct. 1992. - N. K. Jha, I. Pomeranz, S. M. Reddy, and R. J. Miller, ``Synthesis of
multi-level combinational circuits for complete robust path delay fault
testability,''
*IEEE Int. Symp. on Fault-Tolerant Computing*, Boston, July 1992. - J. Rexford and N. K. Jha, ``Algorithm-based fault tolerance for
floating-point operations in massively parallel systems,''
*IEEE Int. Symp. on Circuits & Systems*, San Diego, May 1992. - S.-J. Wang and N. K. Jha, ``Algorithm-based fault tolerance for FFT
networks,''
*IEEE Int. Symp. on Circuits & Systems*, San Diego, May 1992. - S. Bhatia, A. Albicki, and N. K. Jha, ``Aliasing in a linear FSM
used as a multiple-input signature analyzer under uniform
and non-uniform error models,''
*IEEE Int. Symp. on Circuits & Systems*, San Diego, May 1992. - T.-C. Lee and N. K. Jha, ``Redundancy identification and removal in
combinational logic circuits,''
*IEEE Int. Symp. on Circuits & Systems*, San Diego, May 1992. - S. Burns and N. K. Jha, ``A totally self-checking checker for a parallel
unordered coding scheme,''
*IEEE VLSI Test Symp.*, Atlantic City, Apr. 1992. - S. Yajnik and N. K. Jha, ``Design and analysis of fault-detecting and
fault-locating schedules for computation DAGs,''
*Int. Parallel Processing Symp.*, Beverly Hills, CA, Mar. 1992. - B. Vinnakota and N. K. Jha, ``Synthesis of sequential circuits for
parallel scan,''
*The European Conf. on Design Automation*, Brussels, Mar. 1992. - N. K. Jha and S.-J. Wang, ``Design and synthesis of self-checking VLSI
circuits and systems,''
*IEEE Int. Conference on Computer Design*, Cambridge, Mass, Oct. 1991. - R. K. Sitaraman and N. K. Jha, ``Optimal design of checks for error
detection and location in fault tolerant multiprocessor systems,''
*5th Int. Conf. on Fault Tolerant Computing Systems*, Nurenberg, Germany, pp. 396-406, Sept. 1991. - B. Vinnakota and N. K. Jha, ``Design of multiprocessor systems for
concurrent error detection and fault diagnosis,''
*IEEE Int. Symp. on Fault Tolerant Computing*, Montreal, Canada, pp. 504-511, June 1991. - B. Vinnakota and N. K. Jha, ``MACHETE: Synthesis of sequential machines
for easy testability,''
*EDAC/IEEE The European Design Automation Conference*, Amsterdam, The Netherlands, pp. 289-293, Feb. 1991. - B. Vinnakota and N. K. Jha, ``Fault detection in DCVS circuits,''
*CSI/IEEE Int. Symp. on VLSI Design*, New Delhi, India, pp. 29-34, Jan. 1991. - N. K. Jha and Q. Tong, ``Design of robustly testable static CMOS parity
trees derived from binary decision diagrams,''
*IEEE Int. Conf. on Computer Design*, Cambridge, pp. 103-106, Sept. 1990. - B. Vinnakota and N. K. Jha, ``Efficient redundancy utilization in
reconfigurable arrays,''
*Int. Conf. on Fault-Tolerant Systems & Diagnostics*(poster session), Varna, Bulgaria, June 1990. - Q. Tong and N. K. Jha, ``C-testable designs of DCVS binary array
dividers,''
*Int. Conf. on Fault-Tolerant Systems & Diagnostics*, Varna, Bulgaria, pp. 302-311, June 1990. - N. K. Jha, ``Self-checking DCVS circuits,''
*Int. Conf. on Fault-Tolerant Systems & Diagnostics*, Varna, Bulgaria, pp. 312-318, June 1990. - K. Diamantaras and N. K. Jha, ``A new transition count method for
testing of combinational logic circuits,''
*Int. Conf. on Fault-Tolerant Systems & Diagnostics*, Varna, Bulgaria, pp. 218-224, June 1990. - B. Vinnakota and N. K. Jha, ``A dependence graph-based approach to the
design of algorithm-based fault tolerant systems,''
*IEEE Int. Symp. on Fault-Tolerant Computing*, Newcastle, England, pp. 122-129, June 1990. - Q. Tong and N. K. Jha, ``Testing of Zipper CMOS logic circuits,''
*IEEE Int. Symp. on Circuits & Systems*, New Orleans, pp. 9-12, May 1990. - N. K. Jha and Q. Tong, ``Testing of multiple-output domino logic (MODL)
CMOS circuits,''
*IEEE Int. Symp. on Circuits & Systems*, New Orleans, pp. 1-4, May 1990. - A. R. Takach and N. K. Jha, ``Easily testable DCVS multipliers,''
*IEEE Int. Symp. on Circuits & Systems*, New Orleans, pp. 2732-2735, May 1990. - N. K. Jha and Q. Tong, ``Detection of multiple input bridging and
stuck-on faults in CMOS logic circuits using current monitoring,''
*EDAC/IEEE European Design Automation Conf.*, Glasgow, pp. 350-354, Mar. 1990. - N. K. Jha, ``Design of sufficiently strongly self-checking embedded
checkers for systematic and separable codes,''
*IEEE Int. Conf. on Computer Design*, Cambridge, MA, pp. 120-123, Oct. 1989. - B. Vinnakota and N. K. Jha, ``Diagnosability and diagnosis of
algorithm-based fault tolerant systems,''
*IEEE 32nd Midwest Symp. on Circuits & Systems*, Urbana, pp. 28-31, Aug. 1989. - N. K. Jha, ``Design of totally self-checking checkers for Bose-Lin,
Bose and Blaum codes,''
*IEEE 32nd Midwest Symp. on Circuits & Systems*, Urbana, IL, pp. 32-35, Aug. 1989. - N. K. Jha, ``Fault detection in CVS parity trees: application to SSC CVS
parity and two-rail checkers,''
*IEEE Int. Symp. on Fault Tolerant Computing*, Chicago, pp. 407-414, June 1989. - N. K. Jha, ``A technique for converting a single stuck-at fault test set
into a multiple stuck-at fault test set,''
*IEEE VLSI Test Workshop*, Atlantic City, NJ, Apr. 1989. - N. K. Jha, ``Testing of cascode voltage switch parity trees,''
*2nd Int. Workshop on VLSI Design*, Bangalore, India, pp. 266-276, Dec. 1988. - S. Kundu, S. M. Reddy and N. K. Jha, ``On the design of robust multiple
fault testable CMOS combinational logic circuits,''
*IEEE Int. Conf. on Computer-Aided Design*, Santa Clara, CA, pp. 240-243, Nov. 1988. - N. K. Jha, ``A new class of symmetric error correcting/unidirectional
error detecting codes,''
*IEEE Int. Conf. on Computer Design*, Port Chester, NY, pp. 283-286, Oct. 1988. - N. K. Jha, ``SFS/SSC domino-CMOS implementations of TSC circuits,''
*Annual Allerton Conf. on Communications, Control & Computing*, Allerton, IL, pp. 768-777, Oct. 1988. - G. Gupta and N. K. Jha, ``A functional test set for CMOS circuits,''
*Annual Allerton Conf. on Communications, Control & Computing*, Allerton, IL, pp. 1050-1058, Oct. 1987. - N. K. Jha and M. B. Vora, ``A systematic code for detecting
t-unidirectional errors,''
*IEEE Int. Symp. on Fault-Tolerant Computing*, Pittsburgh, PA, pp. 96-101, June 1987. - N. K. Jha, ``Detecting multiple faults in CMOS circuits,''
*IEEE Int. Test Conf.*, Washington, D.C., pp. 514-519, Sept. 1986. - N. K. Jha and J. A. Abraham, ``Techniques for efficient MOS implementation
of totally self-checking checkers,''
*IEEE Int. Symp. on Fault-Tolerant Computing*, Ann Arbor, MI, pp. 430-435, June 1985. - N. K. Jha and J. A. Abraham, ``Totally self-checking CMOS circuits using a
hybrid realization,''
*IEEE Int. Symp. on Fault-Tolerant Computing*, Ann Arbor, MI, pp. 154-158, June 1985. - N. K. Jha and J. A. Abraham, ``Testable CMOS logic circuits under dynamic
behavior,''
*IEEE Int. Conf. on Computer-Aided Design*, Santa Clara, CA, pp. 131-133, Nov. 1984. - N. K. Jha and J. A. Abraham, ``Totally self-checking MOS circuits under
realistic physical failures,''
*IEEE Int. Conf. on Computer Design*, Port Chester, NY, pp. 665-670, Oct. 1984. - N. K. Jha and J. A. Abraham, ``The design of totally self-checking
embedded checkers,''
*IEEE Int. Symp. on Fault-Tolerant Computing*, Orlando, FL, pp. 265-270, June 1984.

- N. Aaraj, A. Raghunathan, and N. K. Jha, ``Virtualization-assisted framework for prevention of software vulnerability based security attacks," Tech. Rep. CE-J07-001, Dept. of Electrical Engineering, Princeton University, Dec. 12, 2007.
- D. Arora, N. Aaraj, A. Raghunathan, and N. K. Jha, ``INVISIOS: A lightweight, minimally intrusive secure execution environment," Tech. Rep. CE-J09-001, Dept. of Electrical Engineering, Princeton University, Jan. 30, 2009.