previous lab | lab schedule | next lab

Use your logic trainers for these activities...

Today's assignment is to wire up and test a 2114 RAM.

The task is complicated because one first must deposit data (supplied from DATA SWITCHES on your trainer) and then read the data by displaying it using the trainer's LEDs. The data in and the data out are on the same wires. We thus must figure out a way to connect and disconnect the DATA SWITCHES from the Input/Output (I/O) lines. This is the role of the 74LS244.

Your task is to deposit as data the address for locations 0000 to 1111. For example, location 0011 should be set to value 0011. Note that these RAMs are 4 bits wide. The parts that you will need to complete this task are a 74LS244 and a 2114 RAM (256 x 4-bit). Data Switches will provide 4-bit address and 4-bit data. Pulse Switches will control the GATE input on the '244 and the CHIP ENABLE input on the 2114. The '244 is needed to buffer the Data Switches from the 2114's I/O lines. When one reads the 2114 (ie., the 2114 is supplying the data) it is essential that no other device (such as a Data Switch) is supplying data.

  1. Begin assignment by attaching low 4 address bits of the 2114 to 4 data switches on your trainer. The higher address bits should be set to 0 by grounding. The Chip Enable should be wired to a Pulse Switch. (Choose an output for the Switch such that the 2114 is disabled when the Pulse Switch is not depressed.)

  2. Wire 4 data switches to 4 buffers on the '244. (Make sure that you use 4 buffers that are all controlled by a single GATE input.) Attach the output of each buffer to a corresponding I/O pin of the 2114. Attach each of the 4 I/O pins to the LED display. Wire the GATE input to a Pulse Switch. (Choose an output for the Switch such that the '244 outputs are disabled when the Pulse Switch is not depressed.)

  3. Wire the Write Enable pin to the enable pin on the 74LS244. This ensures that the buffer is active at the same time as you are writing to the RAM. Think about whether the buffer is active low or active high? Choose the correct pulse switch output so that the buffer becomes active when you press the switch.

  4. One pulse switch should now be connected to the RAM chip select and the other to the buffer/RAM write enable. Depress the Pulse Switches in the right order to deposit data into the first 16 locations of the 2114. Deposit the address as data. (That is, 0000 has value 0000, 0001 has value 0001, etc.) You will need to consult the timing diagrams in the 2114 datasheet to determine the correct order for activating the pulse switches.

  5. Now depress the appropriate Switch or Switches (you figure it out) to read the data from the RAM. Remember that when the chip is not in Write mode it is automatically in Read mode. Once again, consult the timing diagrams. Show your lab instructor.

  6. Create a folder on your desktop called "MAE412_#" where # is your bench number and a subfolder called "Capture". If you don't know your bench number ask any of the Instructors. Diagram this RAM + buffer circuit in ORCAD. (See this document for instructions.) Save your project in the newly created "Capture" folder using the naming convention "2114_bench_#". After having your schematic checked by an AI, submit the DSN file on blackboard. Make sure this file adheres to the same naming convention.

TOOL BOX CHECK. Have your lab instructor check your tool box and chip sets before you leave.


Get parts for the computer (6502 CPU, 6522 VIA, 6551 ACIA, 6116 RAM, 27C64 EPROM, TIL 311 HEX DISPLAY [2 pcs], 1 MHz XTAL CLOCK) and lay them out as compactly as possible on the top sections of your board. (We will be adding more components later.)