The Basics:

Prof. Margaret Martonosi

Engineering Quad, Room B216

Office: (609) 258-1912

Best way to reach me is by e-mail:

martonosi@ee.princeton.edu

2/3/2000: Finish Application example, Talk about Million gate FPGAs, cover details of Virtex FPGAs

SAT slides
Rose, Hill paper on "Future" FPGAs

Virtex Info
Application Note on Virtex configuration
Virtex Memory blocks

2 splash papers, 2 Teramac papers and 1 PAM paper handed out

Rahul Razdan and Michael D. Smith. "High-Performance Microarchitectures with Hardware-Programmable Functional Units," Proc. 27th Annual IEEE/ACM Intl. Symp. on Microarchitecture, pp. 172-180, November 1994.
Rahul Razdan, Karl Brace, and Michael D. Smith. "PRISC Software Acceleration Techniques," Proc. 1994 IEEE Intl. Conf. on Computer Design, pp. 145-149, October 1994.

Carl Ebeling, Darren C. Cronquist, Paul Franklin, Jason Secosky, and Stefan G. Berg. "Mapping Applications to the RaPiD Configurable Architecture" Proc. FCCM, April 1997.

John R. Hauser and John Wawrzynek. "Garp: A MIPS Processor with a Reconfigurable Coprocessor" Proc. FCCM, April 1997.

Goldstein et al. "PipeRench: A Co-Processor for Streaming Multimedia Acceleration".  Proc. 26th International Symposium on Computer Architecture.  May, 1999.

Babb et al. "Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulators".  Proc. FCCM '93.  April, 1993.

Babb et al. "Logic Emulation with Virtual Wires", IEEE Transactions on CAD.

Waingold et al. "Baring it all to Software: Raw Machines", IEEE Computer. Sept '97 pp 86-93.

Specifying and Compiling Applications for RaPiD. Cronquist et al. FCCM 1998.

CPR: A Configuration Profiling Tool.  Cadambi et al.  FCCM 1999.

Parallelizing applications into Silicon.  Babb et al. FCCM 1999.

Fast Compilation for Pipelined Reconfigurable Fabric. Mihai Budiu and Seth Copen Goldstein. FPGA 1999

Managing Pipeline-Reconfigurable FPGAs. S. Cadambi, J. Weener, S. C. Goldstein, H. Schmit, D. E. Thomas. FPGA 1998.

Peter Bellows and Brad Hutchings. "JHDL-An HDL for Reconfigurable Systems"  in Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, April 1998.

Brad Hutchings, Peter Bellows, Joseph Hawkins, Scott Hemmert, Brent Nelson, and Mike Rytting. "A CAD Suite for High-Performance FPGA Design", in Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines. April 1999.

4/11/2000: Zhen Luo on implementing a programmable hardware accelerator for DRC

Z. Luo, Margaret Martonosi and Pranav Ashar, "An Edge-Endpoint-Based Configurable Hardware Architecture for VLSI CAD Layout Design Rule Checking". FCCM99

Peixin Zhong, Margaret Martonosi, Pranav Ashar, and Sharad Malik.  Accelerating Boolean Satisfiability with Configurable Hardware.  IEEE Symposium on FPGAs for Custom Computing Machines (FCCM).  April, 1998.

Peixin Zhong, Margaret Martonosi, Sharad Malik, and Pranav Ashar.  Solving Boolean Satisfiability with Dynamic Hardware Configurations.  Eighth International Workshop on Field Programmable Logic and Applications.  August, 1998. (Also published as Springer-Verlag Lecture Notes in Computer Science Volume 1482).

Sepia.  Shand et al. FCCM 99
Solar Polarimetry: Shand et al. FCCM 98

Kang-Ngee Chia, Hea Joung Kim, Shane Lansing, William H. Mangione-Smith, and John Villasenor "High-Performance Automatic Target Recognition Through Data-Specific VLSI," IEEE Transactions on Very Large Scale Integration Systems, Vol. 6, No. 3, page 364-371, Sep. 98.
 

• Hide Oki on Getting started with Pamette (Feb, 2000)
• Zhen Luo on Pamette designs (Feb, 1999)
• Pamette documentation at SRC