Performance and Synthesis Tools for Adaptive Computing

Principal Investigator: Prof. Margaret Martonosi

Subcontractor: Dr. Maya Gokhale (David Sarnoff Research Center)

Project Summary

Configurable computing has the potential to provide per-application customizations of a compute environment. Through meticulous and time-consuming algorithm mappings, some configurable implementations have demonstrated several orders-of-magnitude performance improvements over more traditional processors. For configurable computing to be widely used however, programmers must be able to harness its application-specific compute power without herculean design efforts.

Although some previous research has looked into automatic compilation and synthesis for configurable systems, the field's current state-of-the-art has serious shortcomings. Mappings of algorithm to configurable hardware are primarily done by hand, in a largely ad-hoc manner. Where tools do exist, they are typically (i) specific to particular problem domains and configurable hardware platforms, (ii) cobbled-together versions of tools taken from other domains, and (iii) re-created or revamped ``on-the-fly'' for each new domain or platform. Just as we no longer expect programmers to routinely program in assembly code, we cannot expect programmers to become part-time hardware designers, or to custom-build specialized tools in order to make use of configurable hardware. Overall, this research can make sweeping changes in how (and to what extent) configurable hardware is used for both commercial and defense applications. Automating the use of configurable hardware will expand its user community and drive technology improvements.

Plans for Upcoming Year

Our research will extend on prior configurable computing work by building an integrated system in which detailed performance monitoring information guides compilation of the application into both executable code and configurable hardware. This work will draw from our past experiences in building performance monitoring hardware and software, and in building compilers for configurable hardware.

A rough diagram of the flow through the proposed system is shown in the accompanying figure. A performance characterization phase identifies points in the code in which configurable hardware may offer significant benefits. We will begin to develop a performance characterization system that can guide synthesis efforts. Our approach will allow for clear performance benefits even on non-annotated code, but may initially be even more effective when used in conjunction with small amounts of user interaction. Following the performance characterization phase, a hardware/software mapping phase uses the collected performance data (as well as user directives/hints) to select code segments and implement them in configurable hardware. Finally, a software compilation phase compiles the remainder of the problem for software execution, including call-out points to invoke the configurable hardware.

Ongoing Research Topics

Applications Research in Configurable Computing

In order to better understand the needs of configurable systems, our project has an active applications component in which we work to develop configurable hardware implementations of key problems. These have included:

Performance Tools for Configurable Computing

Drawing on our prior research experience, our project is producing a set of performance characterization and compilation tools for configurable hardware. Configurable computing mandates specialized performance tools because in this domain, their goal is not simply to identify time-consuming portions of the code. Rather, their goal is to identify time-consuming portions of the code that also have characteristics amenable to implementation in configurable hardware. These characteristics include:

Synthesis Tools for Configurable Computing

Synthesizing configurable hardware also requires special design tools. Ideally, the input to a configurable hardware synthesizer is software written in a high-level programming language. Requiring software engineers to learn hardware description languages is too great a burden. In addition, mapping portions of a problem to configurable hardware is essentially a hardware-software co-synthesis problem, since much of the program may run better as software on a general-purpose processor. Thus, this work will retain a traditional software programming model, while using performance tools to identify key program phases that the synthesis tools will implement in configurable hardware.

Related Publications:

Peixin Zhong, Margaret Martonosi, Sharad Malik and Pranav Ashar. Implementing Boolean Satisfiability in Configurable Hardware. International Workshop on Logic Synthesis. May, 1997.

Peixin Zhong and Margaret Martonosi. Using Reconfigurable Hardware to Customize Memory Hierarchies. SPIE Conference on Reconfigurable Technology for Rapid Product Development and Computing. November, 1996.

Current Support Sources:

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