#!/bin/sh
# This file was generated by:
#
#	Techgen -trans version 7.1 Linux 32 bit - (Wed Nov 28 05:33:58 PST 2007)	Mon Sep 15 14:20:38 2008
#
#------------------------------------------
# BEGIN: Initializations
#
# net file
#
NETFILE="net_1"
#
#
# resistive interconnect variables.  Some of this information is from
# the process file:
#       RINTERPROCESS - process layers for which R will be extracted
#       RINTERHEIGHT - height (thickness) of RINTERPROCESS layers
#       RINTERFILL - grow/shrink amount for RINTERPROCESS layers
#       RINTERBIAS - bias of RINTERPROCESS layers
#       RINTERRES     - sheet resistance of process layers
#       RINTERRANGE  - separation range for 2d capacitance extraction
#       RINTERSEP     - maximum separation for 2d capacitance extraction
#       RTHRESHSEP    - 'infinity' threshhold.  Conductors separated
#                       by this distance are treated as if isolated
# and some from extraction:
#       RINTERCONNECT - extraction layers which correspond to RINTERPROCESS 
#                       layers
# and some from the user
#       RNAMEPREFIX   - resistor name prefixes (these will appear in the dspf)
#       RPROCESSTC    -process layer temperature coefficient TC1,TC2 
#
# The resistive interconnect variables correspond by position, so they must
# all have the same number of elements.  They must also be in top-down process
# order.
#
RINTERPROCESS="mt9 mt8 mt7 mt6 mt5 mt4 mt3 mt2 mt1 poly"
RINTERHEIGHT="1 1 0.36 0.36 0.36 0.36 0.36 0.36 0.3 0.15"
RINTERFILL="0.659 0.659 0.209 0.209 0.209 0.209 0.209 0.209 0.179 0.169"
RINTERBIAS="0 0 0 0 0 0 0 0 0 0"
RINTERRES="0.02 0.02 0.06 0.06 0.06 0.06 0.06 0.06 0.08 10.0"
RINTERRANGE="6.6 6.6 2.1 2.1 2.1 2.1 2.1 1.4 1.2 1.2"
RINTERSEP="6.6 6.6 2.1 2.1 2.1 2.1 2.1 1.4 1.2 1.2"
RTHRESHSEP="6.601 6.601 2.101 2.101 2.101 2.101 2.101 1.401 1.201 1.201"
RINTERCONNECT="metal9_conn metal8_conn metal7_conn metal6_conn metal5_conn metal4_conn metal3_conn metal2_conn metal1_conn poly_conn"
RMODELNAME="mt9 mt8 mt7 mt6 mt5 mt4 mt3 mt2 mt1 poly"
RNAMEPREFIX="a b c d e f g h i j"
RPROCESSTC="- - - - - - - - - -"
#
# RTEXT - contains the text layers which appeared in the extraction
#         and apply to the RINTERCONNECT layers. Each entry must have the form:
#
#               text-layer-name,inter-connect-layer-name
#
#         interconnect-layer-names must appear in the list specified for 
#         RINTERCONNECT
# RTEXTI- contains text layers and corresponding indices into the RINTERCONNECT
#         list. Indices are determined from right to left.  The rightmost
#         RINTERCONNECT layer has an index of 1.
# NRTEXT - text layers attaching to non-resitive layers.
#
RTEXT="Metal9_p_text,Metal9_p,metal9_conn Metal9_p_pintext,Metal9_p,metal9_conn Metal8_p_text,Metal8_p,metal8_conn Metal8_p_pintext,Metal8_p,metal8_conn Metal7_p_text,Metal7_p,metal7_conn Metal7_p_pintext,Metal7_p,metal7_conn Metal6_p_text,Metal6_p,metal6_conn Metal6_p_pintext,Metal6_p,metal6_conn Metal5_p_text,Metal5_p,metal5_conn Metal5_p_pintext,Metal5_p,metal5_conn Metal4_p_text,Metal4_p,metal4_conn Metal4_p_pintext,Metal4_p,metal4_conn Metal3_p_text,Metal3_p,metal3_conn Metal3_p_pintext,Metal3_p,metal3_conn Metal2_p_text,Metal2_p,metal2_conn Metal2_p_pintext,Metal2_p,metal2_conn Metal1_p_text,Metal1_p,metal1_conn Metal1_p_pintext,Metal1_p,metal1_conn"
RTEXTI="Metal9_p_text,10 Metal9_p_pintext,10 Metal8_p_text,9 Metal8_p_pintext,9 Metal7_p_text,8 Metal7_p_pintext,8 Metal6_p_text,7 Metal6_p_pintext,7 Metal5_p_text,6 Metal5_p_pintext,6 Metal4_p_text,5 Metal4_p_pintext,5 Metal3_p_text,4 Metal3_p_pintext,4 Metal2_p_text,3 Metal2_p_pintext,3 Metal1_p_text,2 Metal1_p_pintext,2"
NRTEXT="Metal9_p_text,Metal9_p Metal9_p_pintext,Metal9_p Metal8_p_text,Metal8_p Metal8_p_pintext,Metal8_p Metal7_p_text,Metal7_p Metal7_p_pintext,Metal7_p Metal6_p_text,Metal6_p Metal6_p_pintext,Metal6_p Metal5_p_text,Metal5_p Metal5_p_pintext,Metal5_p Metal4_p_text,Metal4_p Metal4_p_pintext,Metal4_p Metal3_p_text,Metal3_p Metal3_p_pintext,Metal3_p Metal2_p_text,Metal2_p Metal2_p_pintext,Metal2_p Metal1_p_text,Metal1_p Metal1_p_pintext,Metal1_p"
#
# MARKERLAYERS - non-extracted LVS layers.
MARKERLAYERS=
#
# RVIAS - contains the via layers and the interconnect layers to which they
#         apply. Each entry must have the form:
#
#               via-layer-name,interconnect-layer1,interconnect-layer2
#
#         interconnect layers must appear in TINTEREXT
# SRVIAS - list of via names
# RVIAR - contains via resistance.  A dash indicates no resistance.
#         this list must correspond to the RVIAS list
# DAVIAS - contains vias for which the array_vias feature should be disabled.
# ARRAYVIASPACING - contains via,value pairs for the array_vias feature.
# VIAUNITAREA - contains via,value pairs for the via_unit_area feature.
# VIATC - contains via,value1,value2  pairs for the TC1,TC2 feature.
#
BVIAS=
RVIAS="bp_tap,Bondpad,metal9_conn Metal9_v,Metal9_p,metal9_conn Via8,metal9_conn,metal8_conn Metal8_v,Metal8_p,metal8_conn Via7,metal8_conn,metal7_conn Metal7_v,Metal7_p,metal7_conn Via6,metal7_conn,metal6_conn Metal6_v,Metal6_p,metal6_conn Via5,metal6_conn,metal5_conn Metal5_v,Metal5_p,metal5_conn Via4,metal5_conn,metal4_conn Metal4_v,Metal4_p,metal4_conn Via3,metal4_conn,metal3_conn Metal3_v,Metal3_p,metal3_conn via2_cap,metal3_conn,CapMetal via2_out_capInd,metal3_conn,metal2_conn Metal2_v,Metal2_p,metal2_conn Via1,metal2_conn,metal1_conn ind_term1_tap,metal2_conn,ind_term1 ind_term2_tap,metal2_conn,ind_term2 Metal1_v,Metal1_p,metal1_conn cont_poly,metal1_conn,poly_conn cont_pdiff,metal1_conn,pdiff_conn cont_ndiff,metal1_conn,ndiff_conn cont_emit,metal1_conn,npn_emit cont_base,metal1_conn,npn_base cont_coll,metal1_conn,npn_coll ptap_pdiff_conn_ovia,ptap,pdiff_conn psubstrate_ptap_ovia,psubstrate,ptap ntap_ndiff_conn_ovia,ntap,ndiff_conn nwell_conn_ntap_ovia,nwell_conn,ntap nb_tap_nwell_conn_ovia,nb_tap,nwell_conn Nburied_nb_tap_ovia,Nburied,nb_tap"
SRVIAS="bp_tap Metal9_v Via8 Metal8_v Via7 Metal7_v Via6 Metal6_v Via5 Metal5_v Via4 Metal4_v Via3 Metal3_v via2_cap via2_out_capInd Metal2_v Via1 ind_term1_tap ind_term2_tap Metal1_v cont_poly cont_pdiff cont_ndiff cont_emit cont_base cont_coll ptap_pdiff_conn_ovia psubstrate_ptap_ovia ntap_ndiff_conn_ovia nwell_conn_ntap_ovia nb_tap_nwell_conn_ovia Nburied_nb_tap_ovia"
RSOFTVIAS=
RVIAR="- - 0.35 - 0.35 - 1.4 - 1.4 - 1.4 - 1.4 - 1.4 1.4 - 1.4 - - - 10 15 15 - - - - - - - - -"
DAVIAS=
ARRAYVIASPACING=
VIAUNITAREA=
VIATC="- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -"
#
# REXVIASI - Vias which connect one or more resistive layers and corresponding
#            indices into the RINTERCONNECT list.  Indices are determined from
#            right to left.  The rightmost RINTERCONNECT layer's index is 1.
#
REXVIASI="Metal1_v,2 Metal2_v,3 Metal3_v,4 Metal4_v,5 Metal5_v,6 Metal6_v,7 Metal7_v,8 Metal8_v,9 Metal9_v,10 Via1,2,3,t Via3,4,5,t Via4,5,6,t Via5,6,7,t Via6,7,8,t Via7,8,9,t Via8,9,10,t bp_tap,10 cont_base,2 cont_coll,2 cont_emit,2 cont_ndiff,2,t cont_pdiff,2,t cont_poly,1,2,t ind_term1_tap,3 ind_term2_tap,3 via2_cap,4,t via2_out_capInd,3,4,t"
# NEBULAVIAS - Vias which take part in nebula cap extraction and the
#              corresponding indices into the TINTEREXT list.
NEBULAVIAS="Via8,11,12 Via7,10,11 Via6,9,10 Via5,8,9 Via4,7,8 Via3,6,7 via2_out_capInd,5,6 Via1,4,5 cont_poly,3,4 cont_pdiff,2,4 cont_ndiff,2,4"
# PGDBVIAS - Vias which take part in rcx2pgdb and the
#              corresponding indices into the RINTERPROCESS list.
PGDBVIAS="Via8:1:2 Via7:2:3 Via6:3:4 Via5:4:5 Via4:5:6 Via3:6:7 via2_out_capInd:7:8 Via1:8:9 cont_poly:9:10 cont_pdiff:9 cont_ndiff:9"
#
# ALLWIRES - list of connectable layers
#
ALLWIRES="Bondpad CapMetal Metal1_p Metal2_p Metal3_p Metal4_p Metal5_p Metal6_p Metal7_p Metal8_p Metal9_p Nburied ind_term1 ind_term2 metal1_conn metal2_conn metal3_conn metal4_conn metal5_conn metal6_conn metal7_conn metal8_conn metal9_conn nb_tap ndiff_conn npn_base npn_coll npn_emit ntap nwell_conn pdiff_conn poly_conn psubstrate ptap"
#
# NRINTERCONNECT - connectable layers which are non-resistive
# NRINTERPROCESS - non-resistive connectable layers grouped according to common process mapping layers
#
NRINTERCONNECT="Bondpad CapMetal Metal1_p Metal2_p Metal3_p Metal4_p Metal5_p Metal6_p Metal7_p Metal8_p Metal9_p Nburied ind_term1 ind_term2 nb_tap ndiff_conn npn_base npn_coll npn_emit ntap nwell_conn pdiff_conn psubstrate ptap"
NRINTERPROCESS="Bondpad CapMetal Metal1_p Metal2_p Metal3_p Metal4_p Metal5_p Metal6_p Metal7_p Metal8_p Metal9_p nwell_conn,Nburied,psubstrate ind_term1 ind_term2 nb_tap ndiff_conn,pdiff_conn npn_base npn_coll npn_emit ntap ptap"
#
# RRVIAS - vias which connect a pair of resistive layers
# NRVIAS - vias which connect one resistive and one non-resistive layer and
#          the non-resistive layer.
# NNVIASI - vias which connect a pair of non-resistive layers and corresponding
#          indices into the NRINTERPROCESS list.  Indices are determined from
#          left to right.  The leftmost NRINTERPROCESS layer's index is 1
# NNSOFTVIASI - vias which sconnect a pair of non-resistive layers and
#          corresponding indices into the NRINTERPROCESS list.
#
RRVIAS="Via1,metal2_conn,metal1_conn Via3,metal4_conn,metal3_conn Via4,metal5_conn,metal4_conn Via5,metal6_conn,metal5_conn Via6,metal7_conn,metal6_conn Via7,metal8_conn,metal7_conn Via8,metal9_conn,metal8_conn cont_poly,metal1_conn,poly_conn via2_out_capInd,metal3_conn,metal2_conn"
NRVIAS="Metal1_v,Metal1_p Metal2_v,Metal2_p Metal3_v,Metal3_p Metal4_v,Metal4_p Metal5_v,Metal5_p Metal6_v,Metal6_p Metal7_v,Metal7_p Metal8_v,Metal8_p Metal9_v,Metal9_p bp_tap,Bondpad cont_base,npn_base cont_coll,npn_coll cont_emit,npn_emit cont_ndiff,ndiff_conn cont_pdiff,pdiff_conn ind_term1_tap,ind_term1 ind_term2_tap,ind_term2 via2_cap,CapMetal"
NNVIASI="Nburied_nb_tap_ovia,13,17 nb_tap_nwell_conn_ovia,17,12 ntap_ndiff_conn_ovia,23,18 nwell_conn_ntap_ovia,12,23 psubstrate_ptap_ovia,14,24 ptap_pdiff_conn_ovia,24,19"
NNSOFTVIASI=
#
# ACRVIAS - vias for which contact resistance is considered under ?addExplicitVias
# ACRMODEL - model names corresponding to ACRVIAS
# ACRPREFIX - prefices corresponding to ACRVIAS
# ACRVAL - resistance values corresponding to ACRVIAS
# TACRVIAS - vias for which contact resistance is always considered
ACRVIAS="Via8 Via7 Via6 Via5 Via4 Via3 via2_cap via2_out_capInd Via1 cont_poly cont_pdiff cont_ndiff"
ACRMODEL="Via8 Via7 Via6 Via5 Via4 Via3 via2_cap via2_out_capInd Via1 cont_poly cont_pdiff cont_ndiff"
ACRPREFIX="k l m n o p q r s t u v"
ACRVAL="0.35 0.35 1.4 1.4 1.4 1.4 1.4 1.4 1.4 10 15 15"
TACRVIAS=
#
# TINTEREXT - the set of interconnect layers which correspond to the layers 
#             specified in the process file
#
TINTEREXT="metal9_conn metal8_conn metal7_conn metal6_conn metal5_conn metal4_conn metal3_conn metal2_conn metal1_conn poly_conn ndiff_conn,pdiff_conn nwell_conn,Nburied,psubstrate"
#
# SPROCESS - list of layers which are defined as substrate in the process file
#	     (must be in top-down order)
# SINTEREXT -list of extraction layers which correspond to the ${SPROCESS}
#            layers.  The number of elements in the SPROCESS and SINTEREXT
#            lists must be the same
#
SPROCESS="diff sti"
SINTEREXT="ndiff_conn,pdiff_conn nwell_conn,Nburied,psubstrate"
#
# NRPROCESS - non resistive process layers (other than substrate)
# NRINTEREXT -non resistive extraction layers (other than substrate)
# NRINTERRANGE -non resistive separation range for 2d capacitance extraction
# NRINTERSEP -non resistive maximum separation for 2d capacitance extraction
# NRTHRESHSEP-non resistive 'infinity' threshhold.  Conductors separated
#             by this distance are treated as if isolated
#
NRPROCESS=
NRINTEREXT=
NRINTERRANGE=
NRINTERSEP=
NRTHRESHSEP=
#
# TPROCESS - list of layers defined in the process file (must be in top-down
#            order)
# PROCESSGROWAMT-process layer grow amount (must be positive & less than 1/2
#            the minimum design rule separation for the layer)
# PROCESSMINWIDTH-process layer minimum width
# PROCESSMINWIDTH-process layer minimum width
# PROCESSMAXWIDTH-process layer maximum width
# PROCESSEROSION-process layer erosion specification
# PROCESSTOPHEIGHT-process layer top-height specification (top height including
#         metal thickness,relative to deepmost substrate assuming all metal lyrs
#         are present; max possible height in case of non-planar dielectrics
# PROCESSTHICKNESS-process layer thickness (similar to RINTERHEIGHT, covers all proc lyrs)
# TOTALHEIGHT-height of non-substrate process layers and dielectrics
#
TPROCESS="mt9 mt8 mt7 mt6 mt5 mt4 mt3 mt2 mt1 poly diff sti"
PROCESSGROWAMT="- - - - - - - - - - - -"
PROCESSMINWIDTH="0.44 0.44 0.14 0.14 0.14 0.14 0.14 0.14 0.12 0.1 - -"
PROCESSMAXWIDTH="4.4 4.4 1.4 1.4 1.4 1.4 1.4 1.4 1.2 1 - -"
PROCESSEROSION="- - - - - - - - - - - -"
LOADINGEFFECT="- - - - - - - - - - - -"
PROCESSTOPHEIGHT="8.26 6.66 5.06 4.4 3.74 3.08 2.42 1.76 1.1 0.5 0.35 0.35"
PROCESSTHICKNESS="1 1 0.36 0.36 0.36 0.36 0.36 0.36 0.3 0.15 0.005 0.35"
TOTALHEIGHT="7.91"
#
# STMPLAYERS - extraction layers which are used to stamp the layers in STMPTERMS
# STMPTERMS - extraction layers which get stamped with net info
#          each entry must have the form terminal-layer,stamping-layer
# STMPTYPES - either single (1) or multi (2) stamp type
# STMPOELAYERS - other ext_layers
#
STMPLAYERS=
STMPTYPES=
STMPTERMS=
STMPOELAYERS=
#
# 3d capacitance variables. Capacitance will be modeled for pairs of layers
# specified here.
#
# PROCESSCOMB - list of pairs, each entry must have the form: layer1,layer2
#	        and the members of each pair must be specified in top down
#	        order.  This information is extracted from the process file
# PROCESSCOMBRANGE - separation range between pairs specified in the PROCESSCOMB list.
# PROCESSCOMBSEP - separation between pairs specified in the PROCESSCOMB list.
#	        This information is also extracted from the process file
#
PROCESSCOMB="poly,mt1 poly,mt2 mt1,mt2 mt1,mt3 mt2,mt3 mt2,mt4 mt3,mt4 mt3,mt5 mt4,mt5 mt4,mt6 mt5,mt6 mt5,mt7 mt6,mt7 mt6,mt8 mt7,mt8 mt7,mt9 mt8,mt9"
PROCESSCOMBRANGE="0.36 0.36 0.36 0.36 0.42 0.42 0.42 0.42 0.42 0.42 0.42 0.42 0.42 0.42 0.42 0.42 1.32"
PROCESSCOMBSEP="1.2 1.4 1.4 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 6.6 6.6 6.6 6.6"
#
# VARIATIONPARAMETERS - variation file contents for simulating process parameter variations. 
#
VARIATIONPARAM=
#
# Gate specifications. (See capgen -p[a])
#
# PGATE - process gate layers
# EXTGATE - extraction gate layers.  MOS and LDD device layers specified
#           in the process to extraction mapping file
#
PGATE="poly"
EXTGATE=""
#
# Gate capacitance blocking
#
# POLYGATES - gate,poly,diff layer triplets specified in capgen -p options
#
POLYGATES="allGate,poly,diff"
#
# Cap mask layer specifications. (See capgen -c)
#
# EXTMASK - extraction mask layers.  These layers are from the -c file
#           and act as filters to avoid counting again capacitance which
#           has already been included in the various canonical devices
#           Note: number of EXTMASK + EXTGATE + TPROCESS layers may not
#           exceed 16
#
EXTMASK=
#
# PAD specifications
#
PADDEV=
PADTERM=
#
# MOSFET Device specifications
#
MOSDEV="_nmos_12_MOS_559 _nmos_12_hvt_MOS_587 _nmos_12_native_MOS_645 _nmos_25_MOS_673 _nmos_25_native_MOS_701 _pmos_12_MOS_729 _pmos_12_hvt_MOS_757 _pmos_25_MOS_785 _pmoscap_12_MOS_813 _pmoscap_25_MOS_837 _pmoscap_12_3_MOS_861 _pmoscap_25_3_MOS_885 _nmoscap_12_MOS_909 _nmoscap_25_MOS_933 _nmoscap_12_3_MOS_957 _nmoscap_25_3_MOS_981"
MOSSRCDRN="ndiff_conn ndiff_conn ndiff_conn ndiff_conn ndiff_conn pdiff_conn pdiff_conn pdiff_conn pdiff_conn pdiff_conn pdiff_conn pdiff_conn ndiff_conn ndiff_conn ndiff_conn ndiff_conn"
MOSGATE="poly_conn poly_conn poly_conn poly_conn poly_conn poly_conn poly_conn poly_conn poly_conn poly_conn poly_conn poly_conn poly_conn poly_conn poly_conn poly_conn"
MOSSUB="psubstrate psubstrate psubstrate psubstrate psubstrate nwell_conn nwell_conn nwell_conn nwell_conn nwell_conn nwell_conn nwell_conn psubstrate psubstrate psubstrate psubstrate"
MOSTYPE="nmos1v nmos1v_hvt nmos1v_nat nmos2v nmos2v_nat pmos1v pmos1v_hvt pmos2v pmoscap1v pmoscap2v pmoscap1v3 pmoscap2v3 nmoscap1v nmoscap2v nmoscap1v3 nmoscap2v3"
MOSMODEL="nmos1v nmos1v_hvt nmos1v_nat nmos2v nmos2v_nat pmos1v pmos1v_hvt pmos2v pmoscap1v pmoscap2v pmoscap1v3 pmoscap2v3 nmoscap1v nmoscap2v nmoscap1v3 nmoscap2v3"
MOSDF2MODEL="nmos1v nmos1v_hvt nmos1v_nat nmos2v nmos2v_nat pmos1v pmos1v_hvt pmos2v pmoscap1v pmoscap2v pmoscap1v3 pmoscap2v3 nmoscap1v nmoscap2v nmoscap1v3 nmoscap2v3"
MOSLDDDIFFCONTS=
#
# LDD Device specifications
#
LDDDEV=
LDDDRN=
LDDSRC=
LDDGATE=
LDDSUB=
LDDTYPE=
LDDMODEL=
LDDDF2MODEL=
#
# MOS model file (for ADVGEN)
#
MOSMODELFILE=
#
# BJT Device specifications
#
BJTDEV="_vpnp2_BJT_1898 _vpnp5_BJT_1907 _vpnp10_BJT_1916 _pnp_BJT_1925 _npn_BJT_1934"
BJTCOL="psubstrate psubstrate psubstrate psubstrate npn_coll"
BJTBASE="nwell_conn nwell_conn nwell_conn nwell_conn npn_base"
BJTEMIT="pdiff_conn pdiff_conn pdiff_conn pdiff_conn npn_emit"
BJTSUB="- - - - -"
BJTTYPE="vpnp2 vpnp5 vpnp10 pnp npn"
BJTMODEL="vpnp2 vpnp5 vpnp10 pnp npn"
BJTDF2MODEL="vpnp2 vpnp5 vpnp10 pnp npn"
BJTMF=
#
# RESISTOR Device specifications
#
RESDEV="_rndiff_RES_1003 _rndiff_nosal_RES_1042 _rnpoly_RES_1081 _rnpolynw_RES_1120 _rnpoly_nosal_RES_1159 _rnpolynw_nosal_RES_1198 _rpdiff_RES_1237 _rpdiff_nosal_RES_1276 _rppoly_RES_1315 _rppolynw_RES_1354 _rppoly_nosal_RES_1393 _rppolynw_nosal_RES_1432 _rnwellsti_RES_1471 _rnwellod_RES_1510 _resm1_RES_1547 _resm2_RES_1584 _resm3_RES_1621 _resm4_RES_1658 _resm5_RES_1695 _resm6_RES_1732 _resm7_RES_1769 _resm8_RES_1806 _resm9_RES_1843"
RESTERM="ndiff_conn ndiff_conn poly_conn poly_conn poly_conn poly_conn pdiff_conn pdiff_conn poly_conn poly_conn poly_conn poly_conn nwell_conn nwell_conn metal1_conn metal2_conn metal3_conn metal4_conn metal5_conn metal6_conn metal7_conn metal8_conn metal9_conn"
RESSUB="psubstrate psubstrate psubstrate nwell_conn psubstrate nwell_conn nwell_conn nwell_conn psubstrate nwell_conn psubstrate nwell_conn psubstrate psubstrate - - - - - - - - -"
RESTYPE="ressndiff resnsndiff ressnpoly ressnpoly_av2 resnsnpoly resnsnpoly_av2 resspdiff resnspdiff ressppoly ressppoly_av2 resnsppoly resnsppoly_av2 resnwsti resnwoxide resm1 resm2 resm3 resm4 resm5 resm6 resm7 resm8 resm9"
RESMODEL="ressndiff resnsndiff ressnpoly ressnpoly resnsnpoly resnsnpoly resspdiff resnspdiff ressppoly ressppoly resnsppoly resnsppoly resnwsti resnwoxide resm1 resm2 resm3 resm4 resm5 resm6 resm7 resm8 resm9"
RESDF2MODEL="ressndiff resnsndiff ressnpoly ressnpoly resnsnpoly resnsnpoly resspdiff resnspdiff ressppoly ressppoly resnsppoly resnsppoly resnwsti resnwoxide resm1 resm2 resm3 resm4 resm5 resm6 resm7 resm8 resm9"
RESPARAM="1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1"
#
# RES model file (for ADVGEN)
#
RESMODELFILE=
#
# CAP Device specifications
#
CAPDEV="MIMCAP_CAP_1941"
CAPTERM1="CapMetal"
CAPTERM2="metal2_conn"
CAPACONST="-"
CAPSUB="-"
CAPTYPE="mimcap"
CAPMODEL="mimcap"
CAPDF2MODEL="mimcap"
CAPPARAM="1e-15"
CAPMF=
#
# DIODE Device specifications
#
DIODEV="_ndio_DIODE_1882 _pdio_DIODE_1889"
DIOTERM1="psubstrate pdiff_conn"
DIOTERM2="ndiff_conn nwell_conn"
DIOSUB="- -"
DIOTYPE="ndio pdio"
DIOMODEL="ndio pdio"
DIODF2MODEL="ndio pdio"
DIOPARAM="1 1"
DIOMF=
#
# GENERIC Device specifications
#
GENDEV="_nmos_12_iso_Device_617"
GENTERMS="poly_conn,ndiff_conn,ndiff_conn,psubstrate,Nburied"
GENMOS=
GENMOSSRC=
GENMOSDRN=
GENMOSGATE=
GENMOSSUB=
GENMOSSUB2=
GENMOSTYPE=
GENCDEV=
GENCTERMS=
GENCCONST=
GENRDEV=
GENRTERMS=
GENRCONST=
#
# Capgen pax command and .so files
#
COEFF="Y"
CAPCMD="${RCXBIN}/paxfile_coeff"
CAPSO="${RCXBIN}/cap.so"
LVSFILE="${RCXBIN}/lvsfile"
#
# Do not modify the following flags
#
CAP_SW3D="N"
CAP_CN3D="N"
#
# If CAP_CORRECTION=Y, material which forms
# canonical capacitors was included in parasitic
# extraction (subtract canonical capacitance from
# parasitic capacitance to avoid double counting)
#
CAP_CORRECTION="N"
RESMODELNAME="N"
NO_CAP_CORRECTION="N"
CANONICAL_RES_CAPS="Y"
EXTRACT_MOS_DIFFUSION_AP_NW="N"
AP_SCALE_FACTOR=
CDL="N"
NEWPATTERN="Y"
NEBULASCALE=
#
# Variables for virtual metal fill
VMFCONN=
VMFFSEP=
VMFLAYERS=
VMFSSEPMAX=
VMFSSEPMIN=
VMFTYPE=
VMFWIDTH=
#
CONFORMAL="N"
#
LENGTH_UNITS="meters"
CAPGROUNDLAYER="psubstrate"
EXCLUDEGATERES="Y"
CAPS2DVERSION="* caps2d version: 10"
QRCTECHFILEVERSION=
#
# CAPGENOPTS - command-line options used to generate the run-specific
#              RCXspiceINIT/RCXdspfINIT data files
#
CAPGENOPTS="-C -p poly,allGate,diff -canonical_res_caps -length_units meters -exclude_gate_res -cap_ground_layer psubstrate -lvs lvsfile -p2lvs p2lvsfile ."
#
# END: Initializations
#------------------------------------------