A true work of art is a confession -- Albert Camus
Die level leakage power analysis of FinFET circuits considering process variations
Prateek Mishra, Ajay Bhoj and Niraj K. Jha
IEEE International Symposium on Quality Electronic Design(ISQED), San Jose California, March 2010
Low-power FinFET Circuit Synthesis using Surface Orientation Optimization
Prateek Mishra, and Niraj K. Jha
IEEE Design Automation and Test in Europe(DATE), Dresden Germany, March 2010
Evaluation of Multiple Supply and Threshold Voltages for Low-power Circuit Synthesis
Prateek Mishra, Anish Muttreja and Niraj K. Jha
IEEE/ACM International Symposium on Nanoscale Architectures(NANOARCH), Anaheim California, June 2008
Threshold control through multiple supply voltages for power eficient FinFET interconnects
Anish Muttreja,Prateek Mishra and Niraj K. Jha
Int. Conf. on VLSI Design, Hyderabad India, Jan 2008
Low-power FinFET circuit synthesis using multiple supply and threshold voltages
Prateek Mishra and Niraj K. Jha
accpeted in ACM Journal on Emerging Nanotechnologies in Computing.
Simultaneous driver and wire sizing for performance and power optimization
Design with Nanotechnologies - Prof. Niraj Jha
Improving multiprocessor performance by coarse-grain coherence
Computer Architecture - Prof. Margaret Martonosi