| Date |
Topic |
Speaker/s |
Papers |
| 2/8/2002 |
Introduction |
Prof. Lee |
|
| 2/15 |
Graphics A to Z |
Xiao Yang |
|
| 2/22 |
Architectural Latency Estimation with Logical Effort and Wire Delays
Permutation Instructions for Accelerating Software Cryptography |
Prof. Peh
Prof. Lee |
H1-2,
D5-8 |
| 3/1 |
Multithreaded Architectures
Hardware Thread Execution |
Wei Qin
Wang Hangsheng |
A1,3,6
A2,4,5 |
| 3/8 |
Graphics/Multimedia Architecture/Performance |
Subhayu Basu
Vassos Soteriou |
C1-6 |
| 3/15 |
Multimedia Architecture/Performance |
Aaron Cunningham
Michael Cohen |
C7-14 |
| 3/29 |
Cryptography Algorithms
Security Architecture |
Hidekazu Oki
Lin Chang Hong |
RSA, D11
D1-4,9,10,12 ? |
| 4/5 |
Predication
tbd |
Wang Zhenghong
Canturk Isci |
E1-5? |
| 4/12 |
Register Bypass Networks (acceleration techniques)
Memory disambiguation, EPIC architectures |
not yet covered |
B1,2, F1, G1 |
| 4/19 |
|
|
|
| 4/26 |
|
|
|
| 5/3 |
|
|
|
| 5/10 |
|
|
|
| 5/17 |
|
|
|
| 5/24 |
|
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