ELE572: Processor Architectures for New Paradigms

Readings  v0.3, 2/15/2002

                Prof. Ruby Lee
Princeton University, Spring 2002

A.  Multi-threading:

2. H. Akkary and M. Driscol, "A Dynamic Multithreaded Processor", in Proceedings of the 31st Annual International Symposium on Microarchitecture, November 1998.

3. S. Keckler, W. Dally, D. Maskit, N. Carter, A. Chang, and W.S. Lee, "Exploiting Fine-Grain Thread Level Parallelism on the MIT Multi-ALU Processor", in Proceedings of the 25th International Symposium on Computer Architecture, June 1998.

4. P. Marcuello and A. Gonzalez, "Clustered Speculative Multithreaded Processors", in Proceedings of the 1999 International Conference on Supercomputing, April 1999.

5. S. Wallace, B. Calder and D. Tullsen, "Threaded Multiple Path Execution", in Proceedings of the 25th International Symposium on Computer Architecture, June 1998.

6. R. Chappell, J. Stark, S. Kim, S. Reinhardt and Y. Patt, "Simultaneous Subordinate Microthreading (SSMT)", in Proceedings of the 26th International Symposium on Computer Architecture, May 1999.

 
B.  Register Bypassing, Bypass Networks:

2. J. Cruz, A. Gonzalez, M. Valero, N. Topham, "Multiple-Banked Register File Architectures", in Proceedings of the 27th International Symposium on Computer Architecture, June 2000.
 

    C.  Graphics/Multimedia Microarchitecture and ISA (esp. in Architecture Conferences):

1. M. Cox, N. Bhandari and M. Shantz, "Multi-Level Texture Caching for 3D Graphics Hardware", in Proceedings of the 25th International Symposium on Computer Architecture, July 1998.

2. S. Goldstein, H. Schmit, M. Budiu, S. Cadambi, M. Moe, R. Taylor and R. Laufer, "PipeRench: A Co-processor for Streaming Multimedia Acceleration", in Proceedings of the 26th International Symposium on Computer Architecture, May 1999.

3. P. Ranganathan, S. Adve and N. Jouppi, "Performance of Image and Video Processing with General-Purpose Processors and Media ISA Extensions", in Proceedings of the 26th International Symposium on Computer Architecture, May 1999.

4. P. Ranganathan, S. Adve and N. Jouppi, "Reconfigurable Caches and their Application to Media Processing", in Proceedings of the 27th International Symposium on Computer Architecture, June 2000.

5. Christopher J. Hughes, Praful Kaul, Sarita Adve, Rohit Jain, Chanik Park, and Jayanth Srinivasan. "Variability in the Execution of Multimedia Applications and Implications for General-Purpose Architectures",  in Proceedings of the 28th International Symposium on Computer Architecture, June 2001.

6. S. Rixner, W. Dally, U. Kapasi, B. Khailany, A. Lopez-Lagunas, P. Mattson, and J. Owens, "A Bandwidth-Efficient Architecture for Media Processing", in Proceedings of the 31st Annual International Symposium on Microarchitecture, November 1998.

7. R. Lee, M. Smith,  “Media Processing: A New Design Target”, IEEE Micro, Volume 16 Number 4, August 1996, pp. 6-9.

8. R. Lee, “Subword Parallelism with MAX-2”,  IEEE Micro, Volume 16 Number 4,  August 1996, pp. 51-59.

9. Ruby B. Lee,  "Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures", Proceedings of IEEE International Conference on Application-specific Systems, Architectures and Processors, pp.3-14, July 2000.

10. Kevin Scott and Jack Davidson, "Exploring the Limits of Sub-Word Level Parallelism", Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques.

11. Zhen Luo and Ruby B. Lee, "Cost-Effective Multiplication with Enhanced Adders for Multimedia Applications", Proceedings IEEE International Symposium on Circuits and Systems, ISCAS 2000, May 28-31, 2000, Geneva, Switzerland pp. I-651 - I-654.

12. Daniel F. Zucker, Ruby B. Lee, and Michael J. Flynn.  Hardware and Software Cache Pre-fetching Techniques for MPEG Benchmarks. IEEE Transactions on Circuits and Systems for Video Technology.  Vol. 10 No. 5, pp. 782-796.  August 2000.

13. Ruby B. Lee, A. Murat Fiskiran and Abdulla Bubshait.  Multimedia Instructions in IA-64.  Invited paper, Proceedings of 2001 IEEE International Conference on Multimedia and Expo (ICME 2001), Tokyo, Japan, August 22-25, 2001.

14. C. Kozyrakis, S. Perissakis, D. Patterson, T. Anderson, K. Asanovic, M. Cardwell, R. Fromm, J. Golbus, B. Gribstad, K. Keeton, R.Thomas, N. Treuhaft, and K. Yelick, "Scalable Processors in the Billion-Transistor Era: IRAM", Computer, Vol. 30 Issue 9, September 1997.
 

    D.  Security/Cryptography (esp. in Architecture Conferences):

1. S. Kim and A. Somani, "Area Efficient Architectures for Information Integrity in Cache Memories", in Proceedings of the 26th International Symposium on Computer Architecture, May 1999.

2. Lisa Wu, Chris Weaver, and Todd Austin, "CryptoManiac: A Fast Flexible Architecture for Secure Communication", in Proceedings of the 28th International Symposium on Computer Architecture, June 2001.

3. Ki H. Yum, Eun J. Kim, and Chita R. Das, "QoS Provisioning in Clusters: An Investigation of Router and NIC Design", in Proceedings of the 28th International Symposium on Computer Architecture, June 2001.

4. John P. McGregor and Ruby B. Lee. Performance Impact of Data Compression on Virtual Private Network Transactions.  Proceedings of the 25th IEEE Conference on Local Computer Networks, pp. 500-510, November 2000.

5. Ruby B. Lee, Zhijie Shi and Xiao Yang, "Efficient Permutations for Fast Software Cryptography", IEEE Micro, Vol. 21 No. 6, pp. 56-69, December 2001.

6. John P. McGregor and Ruby B. Lee, "Architectural Enhancements for Fast Subword Permutations with Repetitions in Cryptographic Applications", Proceedings of the IEEE International Conference on Computer Design, pp.453-461, September  2001.

7. Xiao Yang and Ruby B. Lee,  "Fast Subword Permutation Instructions Using Omega and Flip Network Stages", Proceedings of International Conference on Computer Design, pp. 15-22, September 17-20, 2000.

8. Zhijie Shi and Ruby B. Lee, "Bit Permutation Instructions for Accelerating Software Cryptography", Proceedings of IEEE International Conference on Application-specific Systems, Architectures and Processors, pp. 138-148, July 10-12, 2000.

9. A. Murat Fiskiran and Ruby B. Lee.  Performance Impact of Addressing Modes on Encryption Algorithms.  Proceedings of the IEEE International Conference on Computer Design, pp. 542-545, Austin, Texas, September  2001.

10. Tommy Thorn, "Programming Languages for Mobile Code", ACM Computing Surveys, Vol. 29 No. 3, pp. 213-239.  September 1997.

11. Gustavus J. Simmons "Symmetric and Asymmetric Encryption" ACM Computing Surveys Vol. 11 No. 4, pp. 305-330.  December 1979.

12. Jerome Burke, John McDonald and Todd Austin, "Architectural Support for Fast Symmetric-Key Cryptography", Proceedings of ASPLOS 2000, pp. 178-189.  November 2000.
 

    E.  Predication and Eager Execution

1. S. A. Mahlke, D. C. Lin, W. Y. Chen, R. E. Hank, and R. A. Bringmann, "Effective Compiler Support for Predicated Execution Using the Hyperblock", in Proceedings of the 25th International Symposium on Microarchitecture, December 1992.

2. G.S. Tyson, "The Effects Of Predicated Execution On Branch Prediction", in Proceedings of the 27th International Symposium on Microarchitecture, November 1994.

3. D.I. August, W.W. Hwu, and S.A. Mahlke, "A Framework for Balancing Control Flow and Predication", in Proceedings of  the 30th International Symposium on Microarchitecture, November 1997.

4. August, D. Connors, S. Mahlke, J. Sias, K. Crozier, B. Cheng, P. Eaton, Q. Olaniran and W. Hwu, "Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture", in Proceedings of the 25th International Symposium on Computer Architecture, June 1998.

5. August, J. Sias, J. Puiatti, S. Mahlke, D. Connors, K. Crozier and W. Hwu, "The Program Decision Logic Approach to Predicated Execution", in Proceedings of the 26th International Symposium on Computer Architecture, May 1999.
 

    F.  Memory Disambiguation and Speculation

1. G. Chrysos and J. Emer, "Memory Dependence Prediction Using Store Sets", in Proceedings of the 25h International Symposium on Computer Architecture, July 1998.

    G. EPIC Architectures

1. Cindy Zheng, Carol Thompson, "PA-RISC to IA-64: Transparent Execution, No Recompilation", IEEE Computer, March 2000.

    H.  Modeling of Latency (Logic and Wires) for Architectural Explorations

1. Ivan Sutherland and Robert Sproull, "Logical Effort: Designing for Speed on the back of an envelop", Advanced Research in VLSI 1991.

2. Scott Rixner, Bill, Dally, et al, "Register Organization for Media Processing", Proceedings of HPCA-6 (High Performance Computer Organization), 2000.