Sharad Malik

http://www.princeton.edu/~sharad


 

Contact Information

Department of Electrical Engineering  

Princeton University  

Princeton, NJ 08544                                                                  

(609) 258-4625

(609) 258-3745 FAX 

sharad@princeton.edu



 

Research Interests

Design methodology for computing systems; system verification; reliable systems.

 

Education

 

Professional Experience

Princeton University Department of Electrical Engineering 

University of California, Berkeley, Computer Science Department 

AT&T Bell Labs, Murray Hill, NJ  

Summer Research Intern - May 1989 to August 1989

 

Awards and Honors

 

Patents and Inventions

 

Program Committee Assignments

 

Editorial Boards

 

Invited Presentations

Talks

§  “Verification of Computer Switching Networks: An Overview,” Invited Talk, Tenth International Symposium on Automated Technology for Verification and Analysis, ATVA 2012

Panels

 

Tutorials

 

Publications 

Books

 

Book Chapters

 

Refereed Journal and Conference Papers

§  “Abstractions for Model Checking SDN Controllers (with D. Sethi and S. Narayana) Formal Methods in Computer-Aided Design, FMCAD, 2013

§  “Model Checking Unbounded Concurrent Lists,” (with D. Sethi and M. Talupur), The 20th International SPIN Workshop on Model Checking of Software (SPIN), 2013

§  “WordRev: Finding Word-Level Structures in a Sea of Bit-Level Gates,” (with W. Li, A. Gascon, P. Subramanyan, W. Y. Tan, A. Tiwari, N. Shankar and S. A. Seshia, HOST, 2013.

§  “Extracting Useful Computation From Error-Prone Processors For Streaming Applications,” (with Y. Yetim and M. Martonosi), Design, Automation & Test in Europe Conference (DATE), 2013

§  “Reverse Engineering Digital Circuits Using Functional Analysis,” (with P. Subramanyan, N. Tsiskaridze, K. Pasricha, D. Reisman and A. Susnea), Design, Automation & Test in Europe Conference (DATE), 2013

§  “Coverage-based Trace Signal Selection for Fault Localisation in Post-Silicon Validation,” (with S. Zhu and G. Weissenbacher), Eighth Haifa Verification Conference, HVC 2012

§  “Verification and Synthesis of Firewalls Using SAT and QBF,” (with S. Zhang, A. Mahmoud and S. Narain), The 2nd International Workshop on Rigorous Protocol Engineering, WRiPE 2012

§  “Efficient Predictive Analysis for Detecting Nondeterminism in Multi-Threaded Programs,” (with A. Sinha and A. Gupta), Formal Methods in Computer-Aided Design, FMCAD, 2012

§  “Verification of Computer Switching Networks: An Overview,” (with S. Zhang and R. McGeer), Invited Paper, Tenth International Symposium on Automated Technology for Verification and Analysis, ATVA 2012

§  “Parallel Assertions for Architectures with Weak Memory Models,” (with D. Schwartz-Narbonne and G. Weissenbacher), Tenth International Symposium on Automated Technology for Verification and Analysis, ATVA 2012

§  “Parameterized Model Checking of Fine Grained Concurrency,” (with D. Sethi, M. Talupur and D. Schwartz-Narbonne), The 19th International SPIN Workshop on Model Checking of Software (SPIN), 2012

§  “PASSERT: A tool for debugging parallel programs,” (with D. Schwartz-Narbonne, F. Liu and D. August), 24th Computer-Aided Verification Conference (CAV), 2012

§  “Specification and Synthesis of Hardware Checkpointing and Rollback Mechanisms,” (with C. Chan, D. Schwartz-Narbonne and D. Sethi), 49th IEEE/ACM Design Automation Conference (DAC), 2012

§  “WOLVERINE: Battling Bugs with Interpolants,” (with G. Weissenbacher and D. Kroening), 18th International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS), 2012

§  “EPROF: An Energy/Performance/Reliability Optimization Framework for Streaming Applications,” (with Y. Yetim and M. Martonosi), IEEE/ACM 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012

§  “Predicting Serializability Violations: SMT-based Search vs. DPOR-based Search,” (with A. Sinha, A. Gupta and C. Wang), Haifa Verification Conference, 2011

§  “Runtime Verification: A Computer Architecture Perspective,” Invited Paper, International Conference on Runtime Verification (RV), 2011

§  “SAT-based Techniques for Determining Backbones for Post-Silicon Fault Localisation,” (with C. S. Zhu, G. Weissenbacher and D. Sethi), IEEE Workshop on High Level Design Validation and Test (HLDVT 2011)

§  “Post-Silicon Fault Localisation Using Maximum Satisfiability and Backbones,” (with S. Zhu, G. Weissenbacher), Formal Methods in Computer-Aided Design (FMCAD), 2011

§  “Specification and Encoding of Transaction Interaction Properties,” (with D. Sethi and Y. Mahajan), Formal Methods in System Design, 2011-10-01, Springer Netherlands, Issn: 0925-9856, Volume: 39, Issue: 2

§  “Parallel Assertions for Debugging Parallel Programs,” (with D. Schwartz-Narbonne, F. Liu, T. Pondicherry and D. August), ACM/IEEE Ninth International Conference on Formal Methods and Models for Codesign, 2011

§  “Predictive Analysis for Detecting Serializability Violations through Trace Segmentation,” (with A. Sinha, A. Gupta and C. Wang), ACM/IEEE Ninth International Conference on Formal Methods and Models for Codesign, 2011

§  “Utility of Transaction-Level Hardware Models in Refinement Checking,” (with Y. Mahajan), IEEE International High Level Design Validation and Test Workshop, 2010.

§  “Combining multi-level decomposition and topological partitioning for PLA's”, (with R. H. Katz), International Conference on Computer-Aided Design, November 87.

 

Others