Sharad Malik

http://www.princeton.edu/~sharad/

Contact Information

Department of Electrical Engineering  

Princeton University

Princeton, NJ 08544

(609) 258-4625

(609) 258-3745 FAX 

sharad@princeton.edu

Research Interests

Design methodology for computing systems; system verification; reliable systems.

Education

• Ph.D. in Computer Science, Univ. of California, Berkeley, December 1990
• M. S. in Computer Science, Univ. of California, Berkeley, May 1987
• Bachelor of Technology in Electrical Engineering, Indian Institute of Technology, New Delhi, May 1985

Professional Experience

Princeton University Department of Electrical Engineering 

• George Van Ness Lothrop Professor of Engineering: September 2005 – present
• September 2006-September 2011: Director, Keller Center for Innovation in Engineering Education (engineering.princeton.edu/ciee)
• November 2009-present: Director, Gigascale Systems Research Center (GSRC) (www.gigascale.org)
• Professor - July 1999 to August 2005
• Associate Professor - July 1996 to June 1999 
• Assistant Professor - February 1991 to June 1996 

University of California, Berkeley, Computer Science Department 

• Post-Graduate Researcher - May 1986 to December 1990
• Teaching Assistant - August 1985 to May 1986

AT&T Bell Labs, Murray Hill, NJ

Summer Research Intern - May 1989 to August 1989

Awards and Honors

• “Efficient Conflict-Driven Learning in a Boolean Satisfiability Solver,” IEEE/ACM International Conference on Computer-Aided Design, Ten Year Retrospective Most Influential Paper Award, 2011
• Princeton University President’s Award for Distinguished Teaching, 2009
• Distinguished Alumni Award, Indian Institute of Technology Delhi, 2009
• Computer Aided Verification Award for Fundamental Contributions with Industrial Impact, 2009
• IBM Faculty Award, 2007 and 2006
• Princeton University, School of Engineering and Applied Sciences, Distinguished Teacher Award, 2005.
• Best Paper Award, IEEE/ACM Design Automation and Test in Europe (DATE), 2003.
• "Power Analysis of Embedded Software: A First Step Towards Software Power Minimization" selected to be included in “The Best of ICCAD – 20 Years of Excellence in Computer-Aided Design,” 2003
• IEEE Fellow, 2002
• Best Paper Award, ACM Design Automation Conference, 1996
• NSF Young Investigator Award, May 1994
• Rheinstein Faculty Award, School of Engineering and Applied Sciences, Princeton University, May 1994
• Engineering Council Excellence in Teaching Award, Princeton University, January 1996, May 1994, May 1993
• Walter C. Johnson Prize for Teaching Excellence, Dept. of Electrical Engineering, Princeton University, May 1993
• NSF Research Initiation Award, August 1992
• Best Paper Award, IEEE International Conference on Computer Design, 1992
• IBM Faculty Development Award, May 1991
• Distinguished Paper Citation, International Conference on Computer-Aided Design, 1991
• University of California Regents Fellowship, 1985 and 1986
• President of India's Gold Medal, IIT Delhi, 1985 for undergraduate academic excellence

Patents and Inventions

• US Patent 7,418,369, August 26, 2008: “Method and System for Efficient Implementation of Boolean Satisfiability”

• US Patent 6,961,916, November 1, 2005: “Placement method for integrated circuit design using topo-clustering”
• US Patent 6,874,135, March 29, 2005: “Method for design validation using retiming”
• US Patent 6,651,234, November 18, 2003: “Partition based decision heuristics for SAT and image computation using SAT and BDDs”
• US Patent 6,449,756, September 10, 2002: “Method for accurate and efficient updates of timing information in logic synthesis, placement and routing for integrated circuit design”
• US Patent 6,442,743, August 27, 2002: “Placement method for integrated circuit design using topo-clustering”
• US Patent 6,367,051, April 2, 2002: “System and method for concurrent buffer insertion and placement of logic gates”
• US Patent 6,286,128, September 4, 2001: “Method for design optimization using logical and physical information”
• US Patent 6,247,164, June 12, 2001: “Configurable hardware system implementing Boolean Satisfiability and method thereof”
• US Patent 6,192,508, Feb 20, 2001: “Method for Logic Optimization for Improving Timing and Congestion During Placement in Integrated Circuit Design”
• US Patent 5,937,183, August 10, 1999: “Enhanced Binary Decision Diagram Based Functional Simulation”
• US Patent 5,841,673, November 24, 1998: “System and method for processing graphic delay data of logic circuit to reduce topological redundancy”
• US Patent 6,038,392, May 27, 1998: “Implementation of Boolean satisfiability with non-chronological backtracking in reconfigurable hardware”
• US Patent 6,035,109, April 22, 1997: “Method for using complete-1-distinguishability for FSM equivalence checking”
• US Patent 5,522,063, May 28, 1996: “Method of Finding Minimum Cost Feedback Vertex Sets for a Graph for Partial Scan Testing without Exhaustive Cycle Enumeration”
• US Patent 5,457,638, October 10, 1995: “Timing Analysis of VLSI Circuits”
• US Patent 5,448,497, September 5, 1995: “Exploiting multi-cycle false paths in the performance optimization of sequential circuits”

Program Committee Assignments

• Runtime Verification, 2012
• Haifa Verification Conference: 2006, 2007, 2008, 2009 Awards Committee Chair.
• Computer-Aided Verification, 2005, 2008 (co-chair)
• SAT 2003, 2004, 2005, 2006
• International Conference on Embedded and Hybrid Systems: 2004
• Design Automation and Test in Europe (DATE): 2004
• Workshop on Bounded Model Checking: 2003, 2004, 2005
• Workshop on Parallel and Distributed Model Checking: 2003, 2004
• EMSOFT: 2003
• ACM Design Automation Conference: 1994, 1995, 1996, 1997, 1998, 1999. Program Co-Chair, DAC 2000 and DAC 2001. Panels Chair 2002. General Chair 2004.
• Constraints in Formal Verification: 2002
• IEEE International Conference on Computer-Aided Design: 1992, 1993, 1994, 1995 (Chair, sub-committee on timing analysis and optimization, 1994, 1995)
• Asia-Pacific Design Automation Conference: 1997, 1998
• International Symposium on Low Power Electronics and Design: 1997, 1999, 2000
• ACM International Workshop on Logic Synthesis: 1991, 1993, 1997 (Technical Program Chair), 1998
• ACM International Workshop on Timing Issues in the Specification, Design and Synthesis of Digital Systems: 1992 (Workshop chair), 1993, 1995, 1997
• ACM Sigplan Workshop on Languages, Compilers and Tools for Embedded Systems: 2000.
• Asynchronous Design Symposium: 2000
• European Design and Test Conference: 1994, 1995
• IEEE International Conference on Computer Design: 1992, 1994
• International Workshop on Low Power Design: 1995
• IEEE International Conference on VLSI Design: 1992

Editorial Boards

• Foundations and Trends in Electronic Design Automation, NOW Publishers, Editor-in-Chief: 2005-2011
• IEEE Transactions on VLSI Systems: 2007-2009
• ACM Transactions on Design Automation of Electronic Systems: 2005-2008
• Formal Methods in System Design, Springer-Verlag: 2005 - present
• IEEE Design and Test: 2001 – 2008
• Guest Editor: Special Issue on “Exploring Synergies for Design Verification,” November-December 2004
• Journal on Satisfiability, Boolean Modeling and Computation (IOS Press): 2003-present
• Design Automation of Embedded Systems, Kluwer Academic Publishers: 1995 - present
• Journal of VLSI Signal Processing, Kluwer Academic Publishers: 1996 - 2005
• Guest Editor: Journal of VLSI Signal Processing, Special Issue on Asynchronous Circuits, Kluwer Academic Publishers, October 1993.

Invited Presentations

Talks

• “Runtime Verification: A Computer Architecture Perspective,” Invited Talk, International Conference on Runtime Verification, 2011, San Francisco.
• “Boolean Satisfiability Solvers and Extensions,” Invited Talk, Advanced Study Institute of the NATO Science for Peace and Security Programme, Tools for Analysis and Verification of Software Safety and Security, August 2011, Marktoberdorf, Germany.
• “Boolean Satisfiability: From Theoretical Hardness to Practical Success,” Invited Seminar, Summer Research Institute, School of Computer and Communication Sciences, École Polytechnique Fédérale de Lausanne (EPFL), June 20, 2011
• “Design Debugging using Boolean Satisfiability,” Invited Talk, First International SAT/SMT Solver Summer School 2011, MIT, June 2011
• “Managing State Explosion through Runtime Verification,” Hardware Verification Workshop (in association with Computer-Aided Verification), July 15, 2010, Edinburgh.
• “Design Methodology and Verification in the Context of Third Party IP,” DARPA Trust Third Party IP Workshop, November 20, 2008
• “SAT and QBF Solvers,” NSF Workshop on Symbolic Computation for Constraint Satisfaction Problems, November 14, 2008
•  “Hardware Verification: Techniques, Methodology and Solutions,”
• Keynote Talk, Tools and Algorithms for the Construction and Analysis of Systems (TACAS), April 4, 2008, Budapest.
• Invited Seminar, Cornell University, May 19, 2008.
• “SAT Solvers: Efficient Implementations,” NSA DoD SAT Workshop, Baltimore, MD, March 3, 2008
• “Verification Driven Formal Architecture and Microarchitecture Modeling,”
• IBM Research, Yorktown Heights, December 12, 2008.
• Intel Annual Symposium, Haifa, July 10, 2007.
• “Optimization and Relaxation in SAT Search,” Workshop on Satisfiability Solvers and Program Verification, Seattle, August 11^th 2006.
• “A Case for the Runtime Validation of Hardware,” Keynote Speaker, IBM Verification Conference, Haifa, November 13^th 2005.
• “Experiences with QBF Solvers,” Workshop on Bounded Model Checking, Edinburgh, July 11^th 2005.
• “The Quest for Efficient SAT Solvers,” Carnegie-Mellon University, School of Computer Science, Distinguished Lecture Series, The Gaschnig/Oakley Memorial Lecture, April 22, 2004.
• “Gigascale Silicon Design: Challenges and Opportunities,” Keynote Speaker, Intel Design and Test Conference, Portland, July 29^th, 2003.
• “Embedded Software Implementation Tools for Fully Programmable Application Specific Systems,” Workshop on Embedded Software (EMSOFT), Grenoble, October 9^th, 2002.
• “The Quest for Efficient SAT Solvers,” Computer-Aided Verification/Conference on Automated Deduction (Joint Invited Talk), Copenhagen, July 29^th, 2002
• “Chaff: Engineering an Efficient SAT Solver.”
• Intel Logic Verification Symposium, 24^th July, 2001, Weizmann Institute of Science, Israel.
• Compaq Corp., Shrewsbury MA, 7^th June, 2001
• “Enabling Fully Programmable Application Specific Solutions through MESCAL: Modern Embedded Systems, Compilers, Architectures and Languages.”
• Motorola Circuits Systems and Architectures Futures Forum, October 16, 2000.
• Enabling Technologies for System-on-Chip Development, Tampere University of Technology, November 15, 2000.
• “Power Analysis for Embedded Software”, Plenary Talk, PATMOS, September 1997.
• “Worst-Case Static Timing Analysis -- From Gates to Instructions”, ACM/IEEE Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, December 1997.

Panels

• “ESL HW/SW Verification: A Reality Check,” Panel Chair, ACM/IEEE Design Automation Conference, June 9, 2011
• National Academy of Engineering, Frontiers of Engineering Education, 2009 (Invited Participant)
• “Why Do We Still Have Bugs? Challenges from Design through System Software”, P=ac^2 Workshop, IBM Research, March 31, 2008
• “Computer-Aided Verification in Many-Core Parallel Software,” Workshop on Exploiting Concurrency Correctly and Efficiently, 2008.
• “Building a Verification Test Plan – Trading Brute Force for Finesse,” Panel Chair, IEEE/ACM Design Automation Conference, 2006
• “Embedded Systems Education,” Panel Chair, IEEE/ACM Design Automation Conference, 2000
•  “Compilers for Systems on a Chip,” Panel Chair, IEEE International Conference on Computer Design, October 1997.

Tutorials

• “CAD Techniques for Embedded Systems”, IEEE VLSI Design, January 1999.
• “Static Timing Analysis of Embedded Software”, ACM Design Automation Conference, June 1997.
• “Optimization Techniques for Low Power VLSI Circuits”, IEEE International Conference on Computer-Aided Design, November 1995.
• “Register Transfer Level Synthesis: From Theory to Practice”, IEEE International Conference on VLSI Design, January 1996.
• “A Survey of Optimization Techniques Targeting Low Power VLSI Circuits”, ACM Design Automation Conference, June 1995.
• “Embedded Systems Performance Analysis”, IEEE International Conference on Computer Design, October 1993.
• “Multi-level Logic Synthesis”, IEEE International Conference on Computer-Aided Design, November 1991, November 1992.
• “Sequential Logic Synthesis”, IEEE International Conference on VLSI Design, January 1991.

Publications 

Books

• Computer Aided Verification, 20th International Conference, CAV 2008, Princeton, NJ, USA, July 7-14, 2008, Proceedings. Lecture Notes in Computer Science 5123 Springer 2008, ISBN 978-3-540-70543-7 (Edited Volume, co-edited with A. Gupta)
• Performance Analysis of Real-Time Embedded Software, (with Yau-Tsun Steven Li), Kluwer Academic Publishers, 1999.

Book Chapters

• Boolean Satisfiability Solvers: Techniques and Extensions, Tools for Analysis and Verification of Software Safety and Security, Editors: T. Nipkow, O. Grumberg, B. Hauptmann, G. Kalus, Publisher: IOS Press, NATO Science for Peace and Security Series, Spring 2012
• Propositional SAT Solving, Handbook of Model Checking (with Joao Marques-Silva and Lintao Zhang), Edited by Ed Clarke, Thomas Henzinger and Helmut Veith, Springer 2011.
• Conflict-Driven Clause Learning, SAT Solvers, Handbook of Satisfiability, (with Joao Marques-Silva and Ines Lynce), Edited by Armin Biere, Hans van Maaren, and Toby Walsh, Production editor Marijn Heule, IOS Press, 2008.
• MADL: An ADL based on a Formal and Flexible Concurrency Model, in Processor Description Languages: Applications and Methodologies, Morgan Kaufman Publishers, (with W. Qin, S. Rajagopalan), Morgan Kaufman, P. Mishra, N. Dutt, Editors, 2008.
• Architecture Description Languages for Retargetable Compilation, (with W. Qin), in The Compiler Design Handbook: Optimizations & Machine Code Generation, CRC Press, Second Edition 2007, Y. N. Srikant and Priti Shankar, Editors.
• A Retargetable VLIW Compiler Framework for DSPs, (with S. Rajagopalan), in The Compiler Design Handbook: Optimizations & Machine Code Generation, CRC Press, Second Edition, 2007, Y. N. Srikant and Priti Shankar, Editors.
• “Boolean Satisfiability: Creating Solvers Optimized for Specific Problem Instances,” (with P. Zhong and M. Martonosi), Reconfigurable Computing: The Theory and Practice of FPGA Computation, Editors: S. Hauck and A. DeHon, Elsevier Publishers, 2007.
• “A Case for Runtime Validation of Hardware,” Hardware and Software, Verification and Testing: First International Haifa Verification Conference, Haifa, Israel, November 13-16, 2005, Revised Selected Papers, Lecture Notes in Computer Science, Springer Volume 3875/2006, Editors:  Shmuel Ur, Eyal Bin, Yaron Wolfsthal
• ZChaff2004: An Efficient SAT Solver, (with Y.Mahajan, Z. Fu), Theory and Applications of Satisfiability Testing, 7th International Conference, SAT 2004. Selected Revised Papers Series: Lecture Notes in Computer Science.
• Analysis of Search Based Algorithms for Satisfiability of Quantified Boolean Formulas Arising from Circuit State Space Diameter Problems, (with D. Tang, Y. Yu and D. Ranjan), Theory and Applications of Satisfiability Testing, 7th International Conference, SAT 2004. Selected Revised Papers Series: Lecture Notes in Computer Science.
• Cache Performance of SAT Solvers: A Case Study for Efficient Implementation of Algorithms,” (with L. Zhang), Theory and Applications of Satisfiability Testing, 6th International Conference, SAT 2003. Santa Margherita Ligure, Italy, May 5-8, 2003 Selected Revised Papers Series: Lecture Notes in Computer Science, Vol.  2919, 2004, Giunchiglia, Enrico; Tacchella, Armando (Eds.)
• Modeling and Integration of Peripheral Devices in Embedded Systems, (with S. Wang and R A Bergamaschi), in Embedded Software for SoC, Kluwer Academic Publishers, 2003, Ahmed Jerraya, Sungjoo Yoo, Norbert Wehn, and Diederik Verkest, Editors.
• SAT and ATPG: Algorithms for Boolean Decision Problems, (with W. Kunz and J. Marques-Silva), in Logic Synthesis and Verification, Kluwer Academic Publishers, 2001, S. Hassoun and T. Sasao, Editors.
• Instruction Level Power Analysis and Optimization of Software, (with V. Tiwari, A. Wolfe and M. T-C. Lee), in    Technologies for Wireless Computing, Kluwer Academic Publishers, 1996, Anantha P. Chandrakasan and Robert W. Brodersen, Editors.
• Code Generation and Optimization Techniques for Embedded Digital Signal Processors, (with Stan Liao, Srinivas Devadas, Kurt Keutzer, Steve Tjiang, Albert Wang, Guido Araujo, Ashok Sudarsanam, Vojin Ziviojnovic, Heinrich Meyr) in Hardware Software Codesign, Kluwer Academic Publishers, NATO-ASI Series, 1996, G. DeMicheli and M. Sami, Editors.
• Performance Analysis of Embedded Systems, (with W. Wolf, A. Wolfe, Y-T S. Li, T-Y Yen), in Hardware Software Codesign, Kluwer Academic Publishers, NATO-ASI Series, 1996, G. DeMicheli and M. Sami, Editors.
• Challenges in Code Generation for Embedded Processors (with Guido Araujo, Srinivas Devadas, Kurt Keutzer, Stan Liao, Ashok Sudarsanam, Steve Tjiang, Albert Wang) in Code Generation for Embedded Processors, Kluwer Academic Publishers, 1995, P. Marwedel and G. Goossens, Editors.

Refereed Journal and Conference Papers

§ “Coverage-based Trace Signal Selection for Fault Localisation in Post-Silicon Validation,” (with S. Zhu and G. Weissenbacher), Eight Haifa Verification Conference, HVC 2012

§ “Verification and Synthesis of Firewalls Using SAT and QBF,” (with S. Zhang and A. Mahmoud), WRiPE 2012: The 2nd International Workshop on Rigorous Protocol Engineering

§ “Efficient Predictive Analysis for Detecting Nondeterminism in Multi-Threaded Programs,” (with A. Sinha and A. Gupta), Formal Methods in Computer-Aided Design, FMCAD, 2012.

§ “Verification of Computer Switching Networks: An Overview,” (with S. Zhang and R. McGeer), Tenth International Symposium on Automated Technology for Verification and Analysis, ATVA 2012

§ “Parallel Assertions for Architectures with Weak Memory Models,” (with D. Schwartz-Narbonne and G. Weissenbacher), Tenth International Symposium on Automated Technology for Verification and Analysis, ATVA 2012

§ “Parameterized Model Checking of Fine Grained Concurrency,” (with D. Sethi, M. Talupur and D. Schwartz-Narbonne), The 19th International SPIN Workshop on Model Checking of Software (SPIN), 2012

§ “PASSERT: A tool for debugging parallel programs,” (with D. Schwartz-Narbonne, F. Liu and D. August), 24^th Computer-Aided Verification Conference (CAV), 2012

§ “Specification and Synthesis of Hardware Checkpointing and Rollback Mechanisms,” (with C. Chan, D. Schwartz-Narbonne and D. Sethi), 49^th IEEE/ACM Design Automation Conference (DAC), 2012

§ “WOLVERINE: Battling Bugs with Interpolants,” (with G. Weissenbacher and D. Kroening), 18th International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS), 2012

§ “EPROF: An Energy/Performance/Reliability Optimization Framework for Streaming Applications,” (with Y. Yetim and M. Martonosi), IEEE/ACM 17th Asia and South Pacific Design Automation Conference, ASP-DAC 2012

§ “Predicting Serializability Violations: SMT-based Search vs. DPOR-based Search,” (with A. Sinha, A. Gupta and C. Wang), Haifa Verification Conference, 2011

§ “Runtime Verification: A Computer Architecture Perspective,” Invited Paper, International Conference on Runtime Verification (RV), 2011

§ “SAT-based Techniques for Determining Backbones for Post-Silicon Fault Localisation,” (with C. S. Zhu, G. Weissenbacher and D. Sethi), IEEE Workshop on High Level Design Validation and Test (HLDVT 2011)

§ “Post-Silicon Fault Localisation Using Maximum Satisfiability and Backbones,” (with S. Zhu, G. Weissenbacher), Formal Methods in Computer-Aided Design (FMCAD), 2011

§ “Specification and Encoding of Transaction Interaction Properties,” (with D. Sethi and Y. Mahajan), Formal Methods in System Design, 2011-10-01, Springer Netherlands, Issn: 0925-9856, Volume: 39, Issue: 2

§ “Parallel Assertions for Debugging Parallel Programs,” (with D. Schwartz-Narbonne, F. Liu, T. Pondicherry and D. August), ACM/IEEE Ninth International Conference on Formal Methods and Models for Codesign, 2011

§ “Predictive Analysis for Detecting Serializability Violations through Trace Segmentation,” (with A. Sinha, A. Gupta and C. Wang), ACM/IEEE Ninth International Conference on Formal Methods and Models for Codesign, 2011

§ “Utility of Transaction-Level Hardware Models in Refinement Checking,” (with Y. Mahajan), IEEE International High Level Design Validation and Test Workshop, 2010.

• “Checking Serializability in Software Transactional Memory,” (with A. Sinha), IEEE International Parallel and Distributed Processing Symposium, 2010.
• “Supporting RTL Flow Compatibility in a Microarchitecture-Level Design Framework,” (with C. Chan, D. Schwartz-Narbonne, and Y. Mahajan), IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis, 2009
•  “Boolean Satisfiability: From Theoretical Hardness to Practical Success,” (with L. Zhang), Invited Paper, Communications of the ACM, Volume 52, Number 8, August 2009.
•  “Declarative Infrastructure Configuration Synthesis and Debugging,” (with S. Narain, G. Levin, V. Kaul), Invited Paper, Journal of Network and Systems Management, Special issue on security configuration management, Springer, DOI 10.1007/s10922-008-9108-y, 2008
• “Runtime Validation of Transactional Memory,” (with K. Chen and P. Patra), 9^th International Symposium on Quality Electronic Design, 2008.
• “Exploiting Circuit Reconvergence through Static Learning in CNF SAT Solvers,” (with Y. Yu and C. Brien), IEEE/ACM 21^st International Conference on VLSI Design, 2008.
• “Runtime Validation of Memory Ordering Using Constraint Graph Checking,” (with K. Chen and P. Patra), IEEE 14^th International Symposium on High-Performance Computer Architecture, 2008.
• “A Hierarchical Modeling Framework for On-Chip Communication Architectures of Multiprocessing SoCs,” (with X. Zhu), ACM Transactions on Design Automation of Electronic Systems, Volume 12, Number 1, 2007.
• “Automating Hazard Checking in Transaction-Level Microarchitecture Models,” (with Y. Mahajan), IEEE Formal Methods in Computer-Aided Design, 2007.
• “Verification Driven Formal Architecture and Microarchitecture Modeling,” (with Y. Mahajan, C. Chan, A. Bayazit and W. Qin), IEEE/ACM MEMOCODE 2007.
• “Extracting Logic Circuit Description from Conjunctive Normal Form Descriptions,” (with Z. Fu),  IEEE/ACM 20^th International Conference on VLSI Design, 2007
• “The Liberty Simulation Environment: A Deliberate Approach to High-Level System Modeling,” (with M. Vachharajani, N. Vachharajani, D. A. Penry, J. A. Blome, and D. I. August), ACM Transactions on Computer Systems (TOCS), Volume 24, Number 3, August 2006.
• “Dependable Multithreaded Processing Using Runtime Validation,” (with K. Chen), 12th Pacific Rim International Symposium on Dependable Computing (PRDC'06), 2006
• “Modeling Operation and Microarchitecture Concurrency for Communication Architectures with Application to Retargetable Simulation,” (with X. Zhu and W. Qin), IEEE Transactions on VLSI Systems, pages 707-716, Volume 14, Number 7, July 2006
• “Understanding the Dynamic Behavior of Modern DPLL SAT Solvers through Visual Analysis,” (with C. Brien), Formal Methods in Computer-Aided Design (FMCAD), 2006
• “On Learning in SMT,” (with Y. Yu), 9th International Conference on Theory and Applications of Satisfiability Testing (SAT), Lecture Notes in Computer Science (LNCS), Volume 4121/2006.
• “Solving Quantified Boolean Formulas with Circuit Observability Don’t Cares,” (with D. Tang), 9th International Conference on Theory and Applications of Satisfiability Testing (SAT), Lecture Notes in Computer Science (LNCS), Volume 4121/2006.
•  “On Solving the Partial MAX-SAT Problem,” (with Z. Fu), 9th International Conference on Theory and Applications of Satisfiability Testing (SAT), Lecture Notes in Computer Science (LNCS), Volume 4121/2006.
•  “Solving the Minimum-Cost Satisfiability Problem using SAT Based Branch-and-Bound Search,” (with Z. Fu), IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2006.
• “Achieving Structural and Composable Modeling of Complex Systems,” (with David I. August, Li-Shiuan Peh, Vijay Pai, Manish Vachharajani, and Paul Willmann), The International Journal of Parallel Programming, Kluwer Academic Publishers, Volume 33, Numbers 2-3, June 2005. Invited Paper.
• “A Study of Architecture Description Languages from a Model Based Perspective,” (with W. Qin), IEEE Workshop on Microprocessor Test and Verification, 2005.
• “Complementary Use of Runtime Validation and Model Checking,” (with A. Bayazit), IEEE/ACM International Conference on Computer-Aided Design, 2005.
• “Bounds on Power Savings using Runtime Dynamic Voltage Scaling: An Exact Algorithm and a Linear-time Heuristic Approximation,” (with F. Xie and M. Martonosi), Proceedings of the International Symposium of Low Power Electronic Design, 2005.
• “Symmetry Reduction in SAT-based Model Checking,” (with D. Tang, A. Gupta and N. Ip),  Lecture Notes in Computer Science, Springer-Verlag, Volume 3576 / 2005, Proceedings of the 17th International Conference on Computer Aided Verification (CAV) 2005. Editors:  Kousha Etessami, Sriram K. Rajamani.
• “Considering Circuit Observability Don’t Cares in CNF Satisfiability,” (with Z. Fu and Y. Yu), DATE 2005.
• “A Technology-aware and Energy-oriented Topology Exploration for On-chip Networks,” (with H. Wang and L-S. Peh), DATE 2005.
• “Verifying the Correctness of Quantified Boolean Formula (QBF) Solvers: Theory and Practice,” (with Y. Yu), ASP-DAC 2005.
• “Intra-program dynamic voltage scaling: Bounding opportunities with analytical modeling,” (with F. Xie and M. Martonosi), p323-367, Volume 1, Issue 3, ACM Transactions on Architecture and Code Optimization (TACO), September, 2004
• “Dynamically Reconfigurable Datapath Co-processor Design for Embedded Systems,” (with Z. Huang, N. Moreano and G. Araujo), ACM Transactions on Embedded Computer Systems, Volume 3 ,  Issue 2  (May 2004), Pages: 361 - 384
• “Facilitating Reuse in Hardware Models with Enhanced Type Inference,” (with M. Vachharajani, N. Vachharajani and D. I. August), IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2004)
• “Modeling Operation and Microarchitecture Concurrency for Communication Architectures with Application to Retargetable Simulation,” (with X. Zhu and W. Qin), IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2004)
• “Analysis of Search Based Algorithms for Satisfiability of Quantified Boolean Formulas Arising from Circuit State Space Diameter Problems,” (with D. Tang, Y.Yu and D. Ranjan), The Seventh International Conference on Theory and Applications of Satisfiability Testing (SAT 2004)
• “A Comparative Study of 2QBF Algorithms,” (with D. Tang and D. Ranjan), The Seventh International Conference on Theory and Applications of Satisfiability Testing (SAT 2004)
• “A Formal Concurrency Model Based Architecture Description Language for Synthesis of Software Development Tools,” (with W. Qin and S. Subramanian), ACM SIGPLAN/SIGBED 2004 Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04)
• “Using a Communication Architecture Specification in an Application-driven Retargetable Prototyping Platform for Multiprocessing,” (with X. Zhu), DATE 2004.
• “Power-driven Design of Router Microarchitectures in On-chip Networks,” with H. Wang and L-S. Peh, MICRO-36, 2003.
• “Generating Operating System based Device Drivers for Peripheral Devices in Embedded Systems,” (with S. Wang), IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2003)
• “Automated Synthesis of Efficient Binary Decoders for Retargetable Software Toolkits,” (with W. Qin), DAC 2003.
• “Cache Performance for SAT Solvers: A Case Study for Efficient Implementation of Algorithms,” (with L. Zhang), SAT 2003.
• “Extracting Small Unsatisfiable Cores from Unsatisfiable Boolean Formulas,” (with L. Zhang), SAT 2003.
• “Compile-Time Dynamic Voltage Scaling: Opportunities and Limits,” (with F. Xie and M. Martonosi), PLDI 2003.
• “Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and Other Applications,” (with L. Zhang), DATE 2003.
• “Flexible and Formal Modeling of Micro-processors with Application to Retargetable Simulation,” (with W. Qin), DATE 2003.
• “Modeling and Integration of Peripheral Devices in Embedded Systems,” (with S. Wang), DATE 2003.
• “A Disciplined Approach to the Development of Platform Architectures,” (with D. I. August, K. Keutzer and A. R. Newton), Invited Article, Microelectronics Journal, Vol. 33 (2002), Pages 881-890.
• “Limits of using signatures for permutation independent Boolean comparison”, (with J. Mohnke and P. Molitor), Formal Methods in System Design, Kluwer Academic Publishers, 2002.
• “Conflict Driven Learning in a Quantified Boolean Satisfiability Solver,” (with L. Zhang), ICCAD 2002.
• “A Hierarchical Modeling Framework for On-Chip Communication Architectures,” (with X. Zhu), ICCAD 2002.
• “Datapath Merging and Interconnect Sharing for Reconfigurable Architectures,” (with N. Moreano, G. Araujo and Z. Huang), In Proceedings of ISSS 2002.
• “Orion: A dynamic power simulator for interconnection networks - power-performance tradeoffs for emerging microprocessor systems,” (with H. Wang, X. Zhu and L-S. Peh),  IEEE MICRO 2002.
• “Design Tools for Application-Specific Embedded Processors,” (with W. Qin, S. Rajagopalan, M. Vachharajani, H. Wang, X. Zhu, D. August, K. Keutzer, and L-S. Peh), Invited Paper, In Proceedings of EMSOFT 2002.
• “From ASIC to ASIP: The Next Design Discontinuity,” (with K. Keutzer and A. R. Newton), Invited Paper, In Proceedings of ICCD 2002.
• “Towards Symmetric Treatment of Satisfaction and Conflict in Quantified Boolean Formula Evaluation,” (with L. Zhang), In Proceedings of the 8^th International Conference on Principles and Practices of Contraint Programming, 2002 (CP2002).
• “A Power Model for Routers: Modeling Alpha 21364 and Infiniband Routers”, (with H. Wang and L-S. Peh), IEEE Hot Interconnects, 2002.
• “The Quest for Efficient Boolean Satisfiability Solvers”, (with Lintao Zhang), Invited Paper and Presentation, In, Proceedings of CADE 2002 and also in Proceedings of CAV 2002.
• “Combining Strengths of Circuit-based and CNF-based Algorithms for a High-Performance SAT Solver,” (with M. Ganai, L. Zhang, P. Ashar and A. Gupta), DAC 2002.

• “Exploiting Operation Level Parallelism through Dynamically Reconfigurable Datapaths,” (with Z. Huang), DAC 2002.

• “A Re-targetable VLIW Compiler Framework for DSPs with Instruction Level Parallelism,” (with S. Rajagopalan, S. P. Rajan, K. Takayama, S. Rigo and G. Araujo), IEEE Transactions on Computer-Aided Design, Volume 20, Number 11, November 2001, pages 1319-1328.

•  “Using Complete 1-Distinguishability for FSM Equivalence Checking”, (with A. Gupta and P. Ashar), ACM Transactions on Design Automation for Electronic Systems, Vol. 6, No. 4, pp. 569-590, October 2001.

• “Application of BDDs in Formal Matching Techniques for Formal Logic Combinational Verification”, (with J. Mohnke and P. Molitor), International Journal on Software Tools for Technology Transfer, Volume 3, Number 2, pages 207-216, May 2001.

• “A Disciplined Approach to the Development of Platform Architectures,” (with D. I. August, K. Keutzer and A. R. Newton), Invited Paper, SASIMI 2001.
• “Partition Based Decision Heuristics for Image Computation Using SAT and BDDs,” (with A. Gupta, Z. Yang, P. Ashar and L. Zhang), ICCAD 2001.
• “Efficient Constraint Driven Learning in a Boolean Satisfiability Solver,” (with L. Zhang, C. Madigan, M. Moskewicz), ICCAD 2001.
• “Accelerating Boolean Satisfiability through Application Specific Processing”, (with Y. Zhao, M. Moskewicz, C. Madigan), ISSS 2001.
• “Matching Architecture to Application via Configurable Processors: A Case Study with the Boolean Satisfiability Problem”, (with Y. Zhao, A. Wang, M. Moskewicz and C. Madigan), ICCD 2001.
• “Retargetable Static Timing Analysis for Embedded Software”, (with K. Chen and D. August), ISSS 2001.
• “Addressing the System-on-a-Chip Interconnection Woes through Communication Based Design”, (with M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, J. Rabaey and A. Sangiovanni-Vincentelli), Invited Paper, DAC 2001.
• “Chaff: Engineering an Efficient SAT Solver”, (with M. W. Moskewicz, C. F. Madigan, Y. Zhao and L. Zhang), DAC 2001.
• “Optimal Live Range Merge for Address Register Allocation in Embedded Programs”, (with G. Ottoni, S. Rigo, G. Araujo and S. Rajagopalan), International Conference on Compiler Construction (CC01), 2001.
• “Using the IMPACT VLIW Compiler Framework to Implement a Compiler for a Fixed Point DSP”, (with S. Rajagopalan, S. P. Rajan, G. Araujo, S. Rigo), SCOPES 2001.
• “Managing Dynamic Reconfiguration Overhead in Systems-on-a-Chip Design Using Reconfigurable Datapaths and Optimized Interconnection Networks”, (with Z. Huang), DATE 2001.
• “System Level Design: Orthogonolization of Concerns and Platform-Based Design”, (with K. Keutzer, J. M. Rabaey, A. R. Newton and A. Sangiovanni-Vincentelli), IEEE Transactions on Computer-Aided Design, Vol. 19, No. 12, December 2000.
• “Exact Memory Size Estimation for Array Computations”, (with Y. Zhao), IEEE Transactions on VLSI Systems, Vol. 8, No. 5, pp 517-521, October 2000.
• “Simultaneous Reference Allocation in Code Generation for Dual Data Memory Bank ASIPs” (with A. Sudarsanam), ACM Transactions on Design Automation for Electronic Systems, Volume 5, Number 2, April 2000.
• “Handling Irregular ILP Within Conventional VLIW Schedulers Using Artificial Resource Constraints”, (with S. Rajagopalan, M. Vachharajani) CASES 2000, November 2000.

• “Incremental CAD”, (with O. Coudert, J. Cong, M. Sarrafzadeh), Invited Paper, IEEE International Conference on Computer-Aided Design 2000.
• “Processor Evaluation in an Embedded Systems Design Environment”, (with T. V. K. Gupta, P. Sharma and M. Balakrishnan), IEEE VLSI 2000.
• “Cache Miss Equations: A Compiler Framework for Analyzing and Tuning Memory Behavior”, (with S. Ghosh and M. Martonosi), ACM Transactions on Programming Languages and Systems (TOPLAS), Vol. 21, No. 4, July 1999, Pages 702-745.
• “Using Configurable Computing to Accelerate Boolean Satisfiability”, (with P. Zhong, M. Martonosi and P. Ashar), IEEE Transactions on Computer-Aided Design, Volume 18, Number 6, pp 861-868, June 1999.
• “Performance estimation of embedded software with instruction cache modeling”, (with Y-T S. Li and A. Wolfe), ACM Transactions on Design Automation of Electronic Systems, Pages 257-279, Volume 4, Number 3, 1999.
• “A Retargetable Compilation Methodology for Embedded Digital Signal Processors Using a Machine-Dependent Code Optimization Library”, (with A. Sudarsanam and M. Fujita), Kluwer Design Automation for Embedded Systems, Volume 4, Number 2/3, March 1999.
• “Paged Absolute Addressing Mode Optimizations for Embedded DSP Programs Using Post-pass Data-flow Analysis”, (with A. Sudarsanam, S. Tjiang and S. Liao) Kluwer Design Automation for Embedded Systems, Volume 4, Number 1, January 1999.
• “Establishing latch correspondence for sequential circuits using distinguishing signatures”, (with J. Mohnke and P. Molitor), Integration, the VLSI Journal, Volume 27, Pages 33-46, 1999.
• “Exact memory size estimation for array computations without loop unrolling”, (with Y. Zhao), Proceedings of the Design Automation Conference, June 1999.
• “Development of a High-Quality Compiler for a Fujitsu Fixed-Point Digital Signal Processor”, (with S.P. Rajan, M. Fujita, A. Sudarsanam), 7th International Workshop on Hardware/Software Codesign, May 1999.
• “Guarded Evaluation: Pushing power management to the Logic Synthesis/Design Level”, (with V. Tiwari and P. Ashar), IEEE Transactions on Computer-Aided Design, October 1998.
• “Code generations for embedded DSP processors”, (with G. Araujo), ACM Transactions on Design Automation for Electronic Systems, April 1998.
• “Precise Miss Analysis for Program Transformations with Caches of Arbitrary Associativity”, (with S. Ghosh and M. Martonosi), Proceedings of the Eighth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), October 1998.                
• “Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability”, (with P. Zhong, M. Martonosi and P. Ashar), DAC 98.
• “Accelerating Boolean Satisfiability with Configurable Hardware”, (with P. Zhong, M. Martonosi and P. Ashar), FCCM 98.
• “Solving Boolean Satisfiability with Dynamic Hardware Configurations”, (with P. Zhong, M. Martonosi and P. Ashar), FPL 98.
• “Performance analysis of embedded software using implicit path enumeration”, (with Y-T Li), IEEE Transactions on CAD, December 1997.
• “Delay abstraction in combinational logic circuits”, (with N. Kobayashi), IEEE Transactions on CAD, October 1997.
• “Power Analysis and Minimization Techniques for Embedded DSP Software”, (with T-C. Lee, V. Tiwari and M. Fujita), IEEE Transactions on VLSI Systems, March 1997.
• “Cinderella: A Retargetable Environment for Performance Analysis of Real-Time Software”, (with Y-T. S. Li and A. Wolfe), Euro-Par 1997.
• “Static Timing Analysis of Embedded Software”, (with M. Martonosi and Y-T Li), ACM Design Automation Conference, June 1997.
• “Toward Formalizing a Simulation Based Verification Methodology”, (with A. Gupta and P. Ashar), ACM Design Automation Conference, June 1997.
• “Cache Miss Equations: An Analytical Representation of Cache Misses”, (with Somnath Ghosh and Margaret Martonosi), ACM International Conference on Supercomputing, 1997. An earlier version was presented at: Workshop on Interaction between Compilers and Computer Architectures, Third International Symposium on High-Performance Computer Architecture (HPCA-3), February 1997.
• “Optimization of Embedded DSP Programs Using Post-pass Data-flow Analysis”, (with Ashok Sudarsanam, Steven Tjiang and Stan Liao), IEEE International Conference on Acoustics, Speech, and Signal Processing, April 1997.
• “Dynamic Power Management for Microprocessors: A Case Study”, (with V. Tiwari and R. Donnelley), IEEE VLSI Design, January 1997.
• “Cache Modeling for Real-Time Software: Beyond Direct Mapped Instruction Caches”, (with Y-T S. Li and A. Wolfe), IEEE Real-Time Systems Symposium, January 1997.
• “Technology mapping for low power”, (with V. Tiwari and P. Ashar), Integration, The VLSI Journal, July 1996
• “Instruction Level Power Analysis and Optimization of Software”, (with V. Tiwari, A. Wolfe and M. T-C. Lee), Journal of VLSI Signal Processing, Kluwer Academic Publishers, August/September 1996.
• “Using Complete-1-Distinguishability for FSM equivalence checking”, (with P. Ashar and A. Gupta), ACM/IEEE International Conference on Computer-Aided Design, November 1996.
• “The Case for Retiming with Explicit Reset Circuitry”, (with V. Singhal and R. K. Brayton), ACM/IEEE International Conference on Computer-Aided Design, November 1996.
• “Instruction set design and optimizations for address computation in DSP architectures”, (with G. Araujo and A. Sudarsanam), International Symposium on System Synthesis, 1996.
• “Using register-transfer paths in code generation for heterogeneous memory-register architectures”, (with G. Araujo and M. T-C. Lee), IEEE/ACM Design Automation Conference June 1996.
• “Practical analysis of cyclic combinational circuits”, (with A. Srinivasan), IEEE Custom Integrated Circuits Conference, 1996.
• “Efficient microarchitecture modeling and path analysis for real-time software”, (with Y-T S. Li and A. Wolfe), IEEE Real-Time Systems Symposium, January 1996.
• “Test Generation for Cyclic Combinational Circuits”, (with A. Raghunathan and P. Ashar), IEEE Transactions on Computer-Aided Design, November 1995.
• “Exploiting multi-cycle false paths in the performance optimization of sequential circuits”, (with P. Ashar and S. Dey), IEEE Transactions on Computer-Aided Design, September 1995.
• “Functional timing analysis using ATPG”, (with P. Ashar and S. Rothweiler), IEEE Transactions on Computer-Aided Design, August 1995.
• “Performance estimation of embedded software with instruction cache modeling”, (with Y-T S. Li and A. Wolfe), ACM/IEEE International Conference on Computer-Aided Design, November 1995.
• “Memory bank and register allocation in software synthesis for ASIPs”, (with A. Sudarsanam), ACM/IEEE International Conference on Computer-Aided Design, November 1995.
• “Fast functional simulation using branching programs”, (with P. Ashar), ACM/IEEE International Conference on Computer-Aided Design, November 1995.
• “Limits of using signatures for permutation independent Boolean comparison”, (with J. Mohnke and P. Molitor), ASP Design Automation Conference, 1995.  Earlier versions have been presented at the following workshops: International Workshop on Logic Synthesis, 1995 and in German as “Ueber den Nutzen von Signaturen beim permutationsunabhaengigen Vergleich Boolescher Funktionen” at the Application of Formal Methods to Hardware Design, Passau, March, 1995.
• “Delay abstraction in combinational logic circuits”, (with N. Kobayashi), ASP Design Automation Conference, 1995.
• “Power Analysis and Low-Power Scheduling Techniques for Embedded DSP Software”, (with T-C. Lee, V. Tiwari and M. Fujita), International Symposium on System Synthesis, 1995.
• “Optimal Code Generation for Embedded Memory Non-Homogeneous Register Architectures”, (with G. Araujo), International Symposium on System Synthesis, 1995.
• “Guarded Evaluation: Pushing power management to the Logic Synthesis/Design Level”, (with V. Tiwari and P. Ashar), International Symposium on Low Power Design, 1995.
• “Performance analysis of embedded software using implicit path enumeration”, (with Y-T Li), ACM Design Automation Conference, June 1995.
• “A Survey of Optimization Techniques Targeting Low Power VLSI Circuits”, (with S. Devadas), ACM Design Automation Conference, June 1995.
• “Prediction of Interconnect Delay in Logic Synthesis”, (with H-F. Jyu), European Design and Test Conference, February 1995.
• “Test Generation for Cyclic Combinational Circuits”, (with A. Raghunathan and P. Ashar), IEEE VLSI Design, January 1995.
• “Power Analysis of Embedded Software: A First Step Towards Software Power Minimization”, (with V. Tiwari and A. Wolfe), IEEE Transactions on VLSI Systems, December 1994.
• “Certified timing verification and the transition delay of a circuit”, (with S. Devadas, K. Keutzer and A. Wang), IEEE Transactions on VLSI Systems, September 1994.
• “Analysis of cyclic combinational circuits”, IEEE Transactions on Computer-Aided Design, July 1994.
• “Event suppression: Improving the efficiency of timing simulation for synchronous digital circuits”, (with S. Devadas, K. Keutzer, and A. Wang), IEEE Transactions on Computer-Aided Design, June 1994.
• “Compilation Techniques for Low Energy: An Overview”, (with V. Tiwari and A. Wolfe), IEEE Solid States Council Symposium on Low Power Electronics, 1994.
• “Power Analysis of Embedded Software: A First Step Towards Software Power Minimization”,  (with V. Tiwari and A. Wolfe), IEEE International Conference on Computer-Aided Design, November 1994. Selected to be included in "The Best of ICCAD – 20 Years of Excellence in Computer Aided Design".
• “Harnessing the performance of microprocessors for real-time applications”,  (with A. Wolfe) Proc. ISCA '94 Workshop on Architectures for Real-Time Applications, April 1994.
• “Statistical timing modeling for logic circuits”, (with H-F. Jyu), ACM Design Automation Conference, June 1994.
• “Implicit computation of minimum-cost feedback-vertex sets for partial scan and other applications”, (with P. Ashar), ACM Design Automation Conference, June 1994.
• “Permutation and phase independent Boolean comparison”, (with J. Mohnke), Integration, The VLSI Journal, North-Holland Publishing, 1993.
• “Computation of floating mode delay in combinational logic circuits: theory and algorithms”, (with S. Devadas, and K. Keutzer), IEEE Transactions on Computer-Aided Design, December 1993.
• “Computation of floating mode delay in combinational logic circuits: practice and implementation”, (with S. Devadas, K. Keutzer and A. Wang), IEEE Transactions on Computer-Aided Design, December 1993.
• “Statistical timing analysis of combinational logic circuits”, (with S. Devadas, H-F. Jyu and K. Keutzer), IEEE Transactions on VLSI Systems, June 1993.
• “Verification of asynchronous interface circuits with bounded wire delays”, (with S. Devadas, K. Keutzer, and A. Wang), Journal of VLSI Signal Processing, October 1993.
• “A synthesis-based test generation and compaction algorithm for multifaults”, (with S. Devadas and K. Keutzer), Journal of Electronic Testing: Theory and Applications, January 1993.
• “Performance optimization of pipelined circuits using peripheral retiming and resynthesis”, (with K. J. Singh, R. K. Brayton and A. Sangiovanni-Vincentelli), IEEE Transactions on Computer-Aided Design, May 1993.
• “Analysis of cyclic combinational circuits”, IEEE International Conference on Computer-Aided Design, November 1993.
• “Statistical timing optimization of combinational logic circuits”, (with H-F Jyu), IEEE International Conference on Computer Design, October 1993.
• “Technology mapping for low power”, (with V. Tiwari and P. Ashar), ACM Design Automation Conference, June 1993.
• “Functional timing analysis using ATPG”, (with P. Ashar and S. Rothweiler), European Conference on Design Automation, Feb. 1993.
• “Permutation and phase independent Boolean comparison”, (with J. Mohnke), European Conference on Design Automation, Feb. 1993.
• “Symbolic minimization of multi-level logic and the input encoding problem”, (with L. Lavagno, R. K. Brayton and A. Sangiovanni-Vincentelli). IEEE Transactions on Computer-Aided Design, July 1992.
• “Exploiting multi-cycle false paths in the performance optimization of sequential circuits”, (with P. Ashar and S. Dey), IEEE International Conference on Computer-Aided Design, Nov. 1992.
• “Verification of asynchronous interface circuits with bounded wire delays”, (with S. Devadas, K. Keutzer, and A. Wang), IEEE International Conference on Computer-Aided Design, Nov. 1992.
• “Statistical timing analysis of combinational logic circuits”, (with S. Devadas, H-F. Jyu and K. Keutzer), International Conference on Computer Design, October 1992.
• “Computation of floating mode delay in combinational logic circuits: practice and implementation”, (with S. Devadas, K. Keutzer and A. Wang), International symposium on Logic Synthesis and Microprocessor Architecture, July 1992.
• “Certified timing verification and the transition delay of a circuit”, (with S. Devadas, K. Keutzer and A. Wang), ACM Design Automation Conference, June 1992.
• “Event suppression: Improving the efficiency of timing simulation for synchronous digital circuits”, (with S. Devadas, K. Keutzer and A. Wang), MIT/Brown VLSI Conference, March 1992.
• “Is redundancy necessary to reduce delay?” (with K. Keutzer and A. Saldanha) IEEE Transactions on Computer-Aided Design , April 1991.
• “Retiming and resynthesis:  Optimization of sequential networks with combinational techniques”, (with E. Sentovich, R. K. Brayton and A. Sangiovanni-Vincentelli). IEEE Transactions on Computer-Aided Design, January 1991.
• “Delay computation for combinational logic circuits: theory and algorithms”, (with S. Devadas and K. Keutzer), IEEE International Conference on Computer-Aided Design, Nov. 1991.
• “A synthesis-based test generation and compaction algorithm for multifaults”, (with S. Devadas and K. Keutzer), Design Automation Conference, June 1991.
• “ MIS-MV: Optimization of multi-level logic with multiple-valued inputs”, (with L. Lavagno, R. K. Brayton and A. Sangiovanni-Vincentelli). International Conference on Computer-Aided Design, November 1990.
• “Performance optimization of pipelined circuits”, (with K. J. Singh, R. K. Brayton and A. Sangiovanni-Vincentelli). International Conference on Computer-Aided Design, November 1990.
• “Algorithms for discrete function manipulation”, (with A. Srinivasan, T. Kam and R. K. Brayton). International Conference on Computer-Aided Design, November 1990.
• “Is redundancy necessary to reduce delay?” (with K. Keutzer and A. Saldanha). Design Automation Conference, June 1990.
• “Retiming and resynthesis:  Optimization of sequential networks with combinational techniques”, (with E. Sentovich, R. K. Brayton and A. Sangiovanni-Vincentelli). Hawaii International Conference on System Sciences, January 1990.
• “Encoding symbolic inputs for multi-level logic implementation”, (with R. K. Brayton and A. Sangiovanni-Vincentelli). IFIP International Conference on Very Large Scale Integration, 1989.
• “Boolean factoring using kernels and rectangle covering”, (with C. L. Berman and N. Maeda). International Symposium on Circuits and Systems, 1989.
• “Logic Verification using binary decision diagrams in a logic synthesis environment”, (with A. Wang, R. K. Brayton and A. Sangiovanni-Vincentelli), International Conference on Computer-Aided Design, November 88.

§ “Combining multi-level decomposition and topological partitioning for PLA's”, (with R. H. Katz), International Conference on Computer-Aided Design, November 87.

Others                                                           

• “Challenges and Solutions for Late- and Post- Silicon Design,” (with J. Rabaey), IEEE Design and Test of Computers, Volume 25, Number 4, July/August 2008. Invited Paper.
•  “A Disciplined Approach to the Development of Architectural Platforms,” (with A. Mihal, C. Kulkarni, C. Sauer, K. Vissers, M. Moskewicz, M. Tsai, N. Shah, S. Weber, Y. Jin, and K. Keutzer). IEEE Design & Test of Computers, 19(6):6--16, November-December 2002.
• “Adapting to a shifting verification scene,” Integrated System Design, CMP Publishers, April 2, 2002.
• “Programmable ASICs to Reduce Costs”, (with D. August, K. Keutzer, R. Newton). EE Times, November 11, 2000.