Past Editor-in-Chief's

Editor-in-Chief 2003-2006

	Nagarajan Ranganathan
Position	Professor
University	University of South Florida, Tampa
Research Interests	VLSI Circuits and System Design VLSI Design Automation Power Estimation and Optimization Low Power Synthesis Interconnects Compilation, heterogeneous Computing Bioinformatics
Department	Computer Science and Engineering
E-Mail Address	ranganat@cse.usf.edu
Homepage	Click Here

Editor-in-Chief 2001-2002

	Eby G. Friedman
Position	Professor
University	University of Rochester
Research Interests	High performance digital and analog CMOS circuit design Interconnect design and modeling Noise aware power and clock distribution design On-chip interconnect and substrate coupling noise modeling and design
Department	Electrical Engineering
E-Mail Address	friedman@ece.rochester.edu
Homepage	Click Here

Editor-in-Chief 1999-2000

	Wayne Wolf
Position	Professor
University	Georgia Tech
Research Interests	embedded computing multimedia systems VLSI computer-aided design
Department	Electrical engineering
E-Mail Address	wayne.wolf@ece.gatech.edu
Homepage	Click Here

Editor-in-Chief 1997-1998

	Bing J. Sheu
Position	Program Director / NCTU Honorary Professor
Company	Taiwan Semiconductor Manufacturing Company
Research Interests	Nanometer CMOS circuits & technologies 22 nm finFETs Predictive Transistor Modeling From imaginary numbers and negative numbers to Universe Globalization Leadership for youth in 21st Century
Function	Design and Technology Platform
E-Mail Address	bjsheu@tsmc.com or bsheu@ee.ncku.edu.tw

Editor-in-Chief 1995-1996

	Donald W. Bouldin
Position	Professor
University	University of Tennessee
Research Interests	VLSI System-on-Chip Design Reconfigurable Computing
Department	Electrical Engineering
E-Mail Address	dbouldin@tennessee.edu
Homepage	Click Here

Editor-in-Chief 1993-1994

	Steve Kang
Position	Chancellor
University	University of California , Merced
Research Interests	Computer aided design of VLSI Low-power VLSI circuits and systems VLSI Reliability IP(Intellectual Property) Modules and Technology Update Statistical design for manufacturability Modeling and simulation of high-speed electronic and optoelectronic integrated circuits and systems Fully optical communication networks
E-Mail Address	chancellor@ucmerced.edu
Homepage	Click Here