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Projects in multiprocessor systems-on-chips (MPSoCs):
MPSoC resources:
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Video Architectures
We have developed new architectures for high-performance video processing,
both for our smart camera application and for other video applications.
With Vijaykrishnan of Penn State, we studied the power and performance
properties of motion estimation algorithms.
Selected papers:
- Shengqi Yang, Wayne Wolf, and N. Vijaykrishnan, "Search speed
and power driven integrated software and hardware optimizations for
motion estimation algorithms," in Proceedings, International
Conference on Multimedia and Exhibition, IEEE, 2004.
- Wayne Wolf, Tiehan Lv, and I. Burak Ozer, "An architectural
design study for a high-speed smart camera," in Proceedings,
4th Workshop on Media and Streaming Processors, IEEE, 2002.
- Jason Schlessman and Wayne Wolf, "Leakage power considerations
for processor array-based vision systems," in Proceedings, SASIMI
04, 2004.
Networks-on-chips
Networks-on-chips are structured interconnect for systems-on-chips. We
studied wave pipelining as a NoC technique and showed that it can save
energy as well as run faster. With Joerg Henkel and Srimiat Chakradar
of NEC, we developed application-specific architectures for networks-on-chips.
Selected papers:
- J.Henkel, W.Wolf, and S.Chakradhar, "On Chip Networks: A scalable
communication-centric embedded system design paradigm," in Procedings,
VLSI Design 2004, IEEE, 2004.
- J. Xu, W. Wolf, T. Lv, J. Henkel, and S. Chakradhar, "A case
study in networks-on-chip design for embedded video," in Proceedings,
DATE 04, IEEE Computer Society Press, 2004.
- Jiang Xu and Wayne Wolf, "A wave-pipelined on-chip interconnect
structure for networks-on-chips," in Proceedings, Hot Interconnects
2003, IEEE, 2003.
Code Compression
We have studied code compression algorithms and architectures for many
years. Most recently, we have concentrated on code compression for VLIW
architectures. We developed profile-driven methods that selectively compress
code. We also showed how to use LZW-style algorithms for code compression
by making use of variable-sized blocks.
Selected papers:
- C. H. Lin, W. Wolf, and Y. Xie, "LZW-based code compression for
embedded systems," in Proceedings, DATE 04, IEEE Computer
Society Press, 2004.
- Yuan Xie, Wayne Wolf, and Haris Lekatsas, "Profile-driven code
compression," in Proceedings, DATE '03, IEEE Computer Society
Press, 2003, pp. 462-467.
- Yuan Xie and Wayne Wolf, "Code compression for VLIW using variable-to-fixed
coding," in Proceedings, ISSS 2002, IEEE, 2002.
Low-Power Design
We developed a bus encoding technique that reduces power consumption
and can be efficiently implemented. This method uses dictionary encoding,
so it does not have to transmit the code words even though they are derived
from the data being transmitted.
Selected papers:
- Tiehan Lv, Joerg Henkel. Haris Lekatsas, and Wayne Wolf, "A
dictionary-based en/decoding scheme for low-power data busses,"
IEEE Transactions on VLSI Systems, 11(5), October 2003, pp. 943-951.
Secure Processors
We developed a new approach to the design of microprocessors that are
resistant to power attacks. A power attack analyzes power supply dynamic
behavior to interpret events within the processor, taking advantage of
the fact that different operations take different amounts of energy. We
use dynamic voltage and frequency scaling to hide the energy consumption
of microprocessor operations:
(c)
2005 IEEE
Our approach makes processor activity less visible with no significant
energy consumption penalty and a modest performance penalty. Dynamic voltage
frequency scaling is well-known and commercially available so this technique
is applicable today.
Selected papers:
- Shengqi Yang, Wayne Wolf, Vijaykrishnan Narayanan, Dimitrios Serpanos,
and Yuan Xie, "Power-attack resistant cryptosystem design: a dynamic
voltage and frequency switching approach," in Proceedings, DATE
'05 Designers Forum, 2005.
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