Topics
Transistor sizing
Example: adder carry chain
Carry chain optimization
Case 1
Case 2
Case 3
Inter-stage effects in transistor sizing
Logical effort
Logical effort gate delay model
Effort delay
Logical effort along a path
Branching effort
Path delay
Sizing the transistors
Example: logical effort
Example, cont’d.
Email: wolf@princeton.edu
Home Page: http://www.ee.princeton.edu/~wolf/vlsi-book
Other information: (c) 2002 Prentice Hall PTR
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