Topics
Verilog
Verilog formulas
Verilog constants
Some useful constructs
Four-valued OR function
Four-valued AND function
Verilog structural model
If statements
Conditional assignments
Loop statement
always statement
Structure of a Verilog model
A synthesizable Verilog archtiecture
Verilog combinational portion
Verilog sequential portion
Testbench structure
Verilog testbed organization
Testbench tester process
Email: wolf@princeton.edu
Home Page: http://www.ee.princeton.edu/~wolf/vlsi-book
Other information: (c) 2002 Prentice Hall PTR
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