Yu-Yuan Chen

Engineering Quad.
Olden Street
Princeton University
Princeton, NJ 08540


Education

Princeton University 9/2006 - Present
5th year PhD, Department of Electrical Engineering
National Taiwan University 9/2000 - 6/2004
B.S., Department of Electrical Engineering

Current research

Hardware architecture security Advisor: Ruby B. Lee
- Improve system security by making minimal modifications to modern computer systems without losing usability and performance. Currently investigate ways to take advantage of multicore CPU to enhance the security of computer systems.

Work experience

Graduate Technical Intern
DEG-SeCoE
Intel, Hillsboro, OR		 Supervisor: Keen Chan
6/2/2008 - 8/29/2008
Security evaluation of Intel Upgrade Service 2008
- Performed the security evaluation of Intel Upgrade Service 2008 architecture, which allows for aftermarket upgrade of platform capabilities after initial sale to end-customers.
- Performed extensive code review, debugging and code tracing. Carried out several attacks including man-in-the-middle attack, flash-overwrite, eavesdropping. Identified several flaws and vulnerabilities in the architecture.

Graduate Technical Intern
CTG-MTL-PSL
Intel, Santa Clara, CA		 Supervisor: Youfeng Wu
6/4/2007 - 8/31/2007
Security issues with Dynamic Binary Translator (DBT)
- Examined potential security issues with DBT. Investigated the operations of DBT, including code discovery, code caching, trace formation, etc., to see if several security functions of the translated program may have been compromised.
- Tested several programs with security features like self-checksumming, anti-debugging, address space randomization, etc., on Intels DBT infrastructure, identified some bugs of current DBT and proposed possible solutions.

Research experience

Analog VLSI Advisor: Shen-Iuan Liu
1/2004 - 6/2004
- Designed a novel burst-mode clock/data recovery circuit.

Electronic devices Advisor: Jenn-Gwo Hwu
9/2003 - 1/2004
- Researched the theory and fabricated the Metal-Oxide-Semiconductor (MOS) temperature sensor.

Nano technology Advisor: Jenn-Gwo Hwu
2/2003 - 6/2003
- Simulated and studied the characteristics of the electron in Single-Electron-Transistor (SET).

Graduate level courses

- Digital Signal Processing
- Computer Architecture
- Analog Integrated Circuit
- Interconnection Networks
- SoC Design Laboratory
- Random Process in Information Systems
- RF Integrated Circuit Design
- Processor Architecture for New Paradigm
- Implementation of Mixed-Signal IPs
- Pervasive Information Systems

Projects

Secret-Protected (SP) architecture on PAX Cryptoprocessor
- Implemented SP architecture on PAX to achieve fast encryption and enhanced security

Interconnection networks
- Designed and simulated a pipelined mesh interconnection network

Cache simulator and Load Value Predictor (LVP)
- Implemented a processor cache simulator and evaluated several LVPs

A Burst-mode Data/Clock Recovery (CDR) Circuit using TSMC 0.35 um Technology
- Designed a novel burst-mode CDR circuit

JPEG Codec System on ARM Platform
- Ported software JPEG code on ARM platform to make us of HW-SW co-design

Wireless Controlled Touch Screen Mini Golf using FPGA
- Designed and implemented a Mini Golf computer game controlled by wireless touch screen