I am working with Prof. David
I. August in Liberty Research
Group on compiler optimization techniques for multi-core
architecture. My research interest includes parallel compiler
optimization, programming language and artificial intelligence. I am
currently working on multithreaded program analysis for optimization
Upcoming Paper Deadlines
Please refer to my Computer Architecture and Compiler Conference Map for upcoming conferences and their deadlines.
Recent Readings
- Automatic Parallelization of Mathematical Models Solved with Inlined Runge-Kutta Solvers, H. Lundvall and P. Fritzson
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Publications
- DAFT: Decoupled Acyclic Fault Tolerance, Yun Zhang, Jae W. Lee, Nick P. Johnson, David I. August, The Nineteenth International Conference on Parallel Architecture and Compilation Techniques (PACT), September 2010
- Liberty Queues for EPIC Architectures
Thomas B. Jablin, Yun Zhang, James A. Jablin, Jialu Huang, Hanjun Kim, and David I. August,
Proceedings of the Eigth Workshop on Explicitly Parallel Instruction Computer Architectures and Compiler Technology (EPIC), April 2010
- Decoupled Software Pipelining Creates Parallelization Opportunities
Jialu Huang, Arun Raman, Yun Zhang, Thomas B. Jablin, Tzu-Han Hung, and David I. August,
Proceedings of the 2010 International Symposium on Code Generation and Optimization (CGO), April 2010.
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Static Data Race Detection for Concurrent Programs with Asynchronous Calls
Vineet Kahlon, Nishant Sinha, Yun Zhang, Erik Kruus, ACM SIGSOFT Symposium on the Foundations of Software Engineering (FSE), August 2009
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Revisiting Sequential Programming Model for the Multi-core
Era(PDF),
M. bridges, N. Vachharajani, Y. Zhang, T. Jablin,
D. I. August, IEEE Micro, January 2008
(IEEE Micro's "Top Picks" special issue for papers "most relevant to
industry and significant in contribution to the field of computer
architecture" in 2007.)
- Revisiting Sequential Programming Model for the Multi-core(PDF),
M. bridges, N. Vachharajani, Y. Zhang, T. Jablin,
D. I. August, Proceedings of the 40th IEEE/ACM International Symposium on Microarchitecture (MICRO), December 2007
- Runtime Empirical Selection of Loop Schedulers on
Hyperthreaded
SMPs(PDF), Y. Zhang,
M. Voss, Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium, April 2005
- An Adaptive OpenMP Loop Scheduler for Hyperthreaded
SMPs(PDF), Y. Zhang, M. Burcea, V. Cheng, R. Ho, M.
Voss, Proceedings of the 17th International Conference for Parallel and Distributed Computing Systems, September 2004
Talks and Presentations
- My talk slides on alias analysis using separation logic in my generals exam (qualification exam in Princeton) can be
found here
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Research Links
Crazy Research Ideas
Here I am listing a couple of not yet matured researched ideas and
crazy thoughts that I
may be interested to step in later. If you have any thoughts or ideas
or suggestion, please contact with me ~
- Online pointer analysis using static predicates and runtime libraries?
We have spent tremendous efforts on
pointer analysis for decades yet still not making pratical progress.
Why? Shall we simply abandon the current pointer
memory management system or shall we look for static-runtime hybrid pointer
analysis?
- Is there a way to predict the performance of dynamic optimization statically?
When we cannot find anything statically, we always want
to go online. But how do we know whether online optimization is
gonna work as we expect? How do we know whether the price we pay can come
back? Is there a way that can prevent us from
making efforts in vain at the very beginning?
- Since we have machines with 100,000 processors, why do we still want to
do speculation? We can just throw two or more versions there and
pick the right one later. We dont know how to use those idling 99,
999 processors anyway. This leads to a fundamental question: do we
want to do things 100% correctly at the beginning, or do we allow ourselves
to make some tolerable mistakes and being able to fix it at a very
low cost?