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With increasing complexity of gigascale systems chip multiprocessors have started to display complex and heterogeneous behavior in which each core might vary in power, performance and reliability characteristics. Likewise, applications also display heterogeneous performance and reliability characteristics. Furthermore, some applications (e.g. streaming multimedia applications) can tolerate some degree of unreliability in exchange for improved performance or power profiles. For these cases, heterogeneous hardware might be even advantageous. I am currently working on programming interfaces for error tolerant architectures. These interfaces let us observe the effects of different protection schemes that enables applications to produce acceptable output in the face of errors. The techniques I develop do not require drastic changes on existing applications and minimizes occurrence of catastrophic errors such as segmentation faults and infinite loops. Publications:
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