Scalable Coherent Interface

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SCI, for Scalable Coherent Interface, is a high-speed interconnect standard for shared memory multiprocessing and message passing. The IEEE Std 1596-1992, IEEE Standard for Scalable Coherent Interface [SCI] was approved by the IEEE standards board on March 19, 1992. The goal was to create an interconnect that would scale well, provide system-wide coherency and a simple interface; i.e. a standard to replace buses in multiprocessor systems without the inherent scalability and performance limitations of buses. The working group soon realized that any form of buses would not suffice and came up with the idea of using point-to-point communication in the form of insertion rings as the right way to go. This approach avoids the lumped capacitance, limited physical length/speed of light problems and stub reflections in addition to allowing parallel transactions. The use of insertion rings is credited to Manolis Katevenis who suggested it at one of the early meetings of the working group. The working group for developing the standard was led by David B. Gustavsson (chair) and David V. James (Vice Chair).

Contents

History

SCI originally developed from the fabled Futurebus (IEEE 896) program that started in 1987. Soon after the project started, members of the engineering teams predicted it would already be too slow for the high-end marketplace by the time it would be released in the early 1990s. In response, a group spun off to form the SCI standard targeted at this market. SCI was essentially a subset of Futurebus features that could be easily implemented at high speed, along with a few minor additions to make it easier to connect to other systems, such as VMEbus. Most of the individuals behind the standard had their background from high-speed buses. Representatives from many companies in the IT industry and research community were active participants in the working group. Among those were people from Amdahl, Apple Computer, BB&N, Hewlett Packard, CERN, Dolphin Server Technology, Cray Research, Sequent, AT&T, Digital Equipment Corporation, McDonnel Douglas, National Semiconductor, Stanford Linear Accelerator Center, Tektronix, Texas Instruments, Unisys, University of Oslo, University of Wisconsin.

The original intent was to create a single standard that could be used for all buses in the computer. To quote from the standards website, SCI is a: combination computer backplane bus, processor memory bus, I/O bus, high performance switch, packet switch, ring, mesh, local area network, optical network, parallel bus, serial bus, information sharing and information communication system that provides distributed directory based cache coherency for a global shared memory model and uses electrical or fiber optic point-to-point unidirectional cables of various widths.

A large part of the intellectual work must be credited to David V. James as the major contributor for writing the specifications including the executable C-code. Stein Gjessing’s group at the University of Oslo used formal methods to verify the coherence protocol and Dolphin Server Technology implemented a node controller chip including the cache coherence logic.

Different versions and derivatives of SCI have been implemented and used in different applications by companies like Dolphin Interconnect Solutions, Convex, Data General (used cache controller and link controller chips from Dolphin AViiON), Sequent and Cray Research. Dolphin Interconnect Solutions [1] implemented a PCI and PCI-Express connected derivative of SCI that provides non-coherent shared memory access. This implementation was used by Sun Microsystems Sun Microsystems for its high-end clusters, Thales Group and several others including volume applications for message passing within HPC clustering and medical imaging. It was also used by Sequent Computer Systems as the processor memory bus in their NUMA-Q systems. Lately, Numascale [2] has developed a derivative to connect with coherent HyperTransport.

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