Computer Engineering

Princeton University
CAD Projects
at Princeton University

RMRLS 0.2 : Year 2007
 Reed-Muller Reversible Logic Synthesis tool (a.k.a. RELOS) is a tool for the synthesis of reversible functions based on positive-polarity Reed-Muller expressions. The second release of RMRLS features reversible logic synthesis with SWAP, Fredkin, and Peres gates. This work was done under the supervision of Professor Niraj K. Jha. The student involved was James Donald.

Here are the references associated with this work:
  1. J. Donald and N. K. Jha. "Reversible Logic Synthesis with Fredkin and Peres Gates." ACM Journal Emerging Technologies Computing Systems, 2008 (accepted for publication).
  2. P. Gupta, A. Agrawal, and N. K. Jha. "An Algorithm for Synthesis of Reversible Logic Circuits." IEEE Trans. Computer-Aided Design, vol. 24, no. 1, Nov. 2006.
  3. A. Agrawal and N. K. Jha, "Synthesis of Reversible Logic." Design Automation and Test in Europe Conf., Feb. 2004.

ALLCN : Year 2007
 ALLCN is a logic-to-layout synthesis tool for carbon nanotube based field-effect transistors (CNFETs). It can automatically generate a mid-sized CNFET-based circuit layout from its logic implementation. ALLCN is built on top of existing CAD tools including Magic, TimberWolf and YACR. This project was done under the supervision of Professor Niraj K. Jha, Princeton University. The graduate student involved was Wei Zhang. Another graduate student, Kate Muldawer, created the standard cells 3nor, inor3 and mux2.

Here is the reference associated with this work:

  1. Wei Zhang, and Niraj K. Jha, "ALLCN: an automatic logic-to-layout tool for carbon nanotube based nanotechnology," in Proc. Int. Conf. Computer Design, Oct. 2005, pp. 281-288.

TELS/MALS : Year 2006
 TELS (MALS) is a multi-level threshold (majority) logic synthesis tool integrated on top of SIS. They are useful for the following nanotechnologies: resonant tunneling diodes, quantum cellular automata, single electron transistors, and tunneling phase logic. This project was done under the supervision of Professor Niraj K. Jha, Princeton University. The graduate students involved were Rui Zhang, Pallav Gupta and Lin Zhong.

Here are the references associated with this work:

  1. R. Zhang, P. Gupta, L. Zhong, and N. K. Jha, "Threshold network synthesis and optimization and its application to nanotechnologies," IEEE Trans. Computer-Aided Design, vol. 24, no. 1, pp. 107-118, Jan. 2005.
  2. R. Zhang, P. Gupta, L. Zhong, and N. K. Jha, "Synthesis and optimization of threshold logic networks with application to nanotechnologies," in Proc. Design Automation & Test Europe Conf., Feb. 2004, pp. 904-909.
  3. R. Zhang, P. Gupta, and N. K. Jha, "Synthesis of majority and minority networks and its applications to QCA, TPL and SET based nanotechnologies," in Proc. Int. Conf. VLSI Design, Jan. 2005, pp. 229-234.
  4. P. Gupta, R. Zhang, and N. K. Jha, "An automatic test pattern generation framework for combinational threshold logic networks," in Proc. IEEE Int. Conf. Computer Design, Oct. 2004, pp. 540-543.
  5. R. Zhang and N. K. Jha, “State Encoding of Finite-state Machines Targeting Threshold and Majority Logic Based Implementations with Application to Nanotechnologies,?in Proc. Int. Conf. VLSI Design, Jan. 2006, pp. 317-322.
  6. R. Zhang and N. K. Jha, "Threshold/majority logic synthesis and concurrent error detection targeting nanoelectronic implementations," in Proc. ACM Great Lakes Symp. VLSI, Apr. 2006.
RMRLS 0.1 : Year 2006
 Reed-Muller Reversible Logic Synthesis tool (aka RELOS) is a tool for the synthesis of reversible functions based on positive-polarity Reed-Muller expressions. This work was done in Princeton University under the supervision of Professor Niraj K. Jha. The students involved were Abhinav Agrawal and Pallav Gupta.

Here are the references associated with this work:
  1. P. Gupta, A. Agrawal, and N. K. Jha. "An Algorithm for Synthesis of Reversible Logic Circuits." IEEE Trans. Computer-Aided Design, vol. 24, no. 1, Nov. 2006.
  2. A. Agrawal and N. K. Jha, "Synthesis of Reversible Logic." Design Automation and Test in Europe Conf., Feb. 2004.

Embedded StrongArm Energy Simulator (EMSIM-2.0) : Year 2003
EMSIM is an energy simulation framework that simulates a simple embedded system featuring StrongARM microprocessor and Linux OS.The purpose of building this simulation framework is to facilitate our research in the following areas:
1) To study the effects of an OS on the overall system energy consumption.
2) To characterize and macro-model the energy consumption of Linux OS.
3) To study the effects of OS related software architectural transformation.

Author: Tat K. Tan

The Embedded Systems Synthesis Benchmarks Suite (E3S) is a collection of benchmarks based on embedded processor and task information from the Embedded Microprocessor Benchmark Consortium (EEMBC). E3S was developed for use in system-level allocation, assignment, and scheduling research. The current version, 0.9, contains contains 17 processors, e.g., the AMD ElanSC520, Analog Devices 21065L, the Motorola MPC555, and the Texas Instruments TMS320C6203. These processors are characterized based on the measured execution times of 47 tasks, power numbers derived from processor datasheets, and additional information, e.g., die sizes, some of which were necessarily estimated, and prices gathered by emailing and calling numerous processor vendors. In addition, E3S contains communication resources modeling a number of different busses, e.g., CAN, IEEE1394, PCI, USB 2.0, and VME.
Author: Robert Dick
TGG is a task graph generation program. (Also known as a task graph extractor.) Real-time embedded systems are often written in C and have to be manually transformed into task graphs to depict the dependencies within the system software. This is a difficult, time-consuming and error-prone step in system level design. To aid designers, we have developed a tool which can read C source code and determine dependencies automatically. The tool may be downloaded for free via the link provided below. The program is small (around 10,000 lines of code), easy to install, and includes examples. Details and disclaimer.
Author: Keith Vallerio
TGFF creates problem instances for use in allocation and scheduling research. It has the ability to generate independent tasks as well as task sets which are composed of partially ordered task graphs. A complete description of a scheduling problem instance is created, including attributes for processors, communication resources, tasks, and inter-task communication.
Authors: Robert Dick , Keith Vallerio, and David Rhodes
Cinderella
 A tool for determining a tight bound on a program's best case and worst case execution times. The tool performs a static analysis of the program's executable code, models the instruction cache memory and computes the bound through the use of integer linear programming.
Author: Yau-Tsun Steven Li
SPAM
 The SPAM Project is a joint project of the Advanced Technology Group of Synopsys, Inc., Professor Sharad Malik at Princeton University, DSP Group headed by Professor Heinrich Meyr at Aachen University of Technology, Germany, and Professor Srinivas Devadas at MIT (Research Laboratory of Electronics). The goal is to develop a portable optimizing compiler for embedded processors.
Also involved: Guido Araujo and Ashok Sudarsanam
HML
 A Novel Hardware Description Language With Automatic Typing and Polymorphic Functionality. HML is also integrated as a front-end to VHDL.
Author: Yanbing Li

This page is maintained by Prof. Niraj Jha.